Commit 0ed66bef authored by Ludovic Desroches's avatar Ludovic Desroches Committed by Nicolas Ferre
Browse files

ARM: at91: fix infinite loop in at91_irq_suspend/resume 



Fix an infinite loop when suspending or resuming a device with AIC5.

Signed-off-by: default avatarLudovic Desroches <ludovic.desroches@atmel.com>
Acked-by: default avatarJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: default avatarNicolas Ferre <nicolas.ferre@atmel.com>
parent 647f8d94

arch/arm/mach-at91/irq.c

+8 −12
Original line number Diff line number Diff line
@@ -92,23 +92,21 @@ static int at91_aic_set_wake(struct irq_data *d, unsigned value) 


void at91_irq_suspend(void)

{

	int i = 0, bit;

	int bit = -1;



	if (has_aic5()) {

		/* disable enabled irqs */

		while ((bit = find_next_bit(backups, n_irqs, i)) < n_irqs) {

		while ((bit = find_next_bit(backups, n_irqs, bit + 1)) < n_irqs) {

			at91_aic_write(AT91_AIC5_SSR,

				       bit & AT91_AIC5_INTSEL_MSK);

			at91_aic_write(AT91_AIC5_IDCR, 1);

			i = bit;

		}

		/* enable wakeup irqs */

		i = 0;

		while ((bit = find_next_bit(wakeups, n_irqs, i)) < n_irqs) {

		bit = -1;

		while ((bit = find_next_bit(wakeups, n_irqs, bit + 1)) < n_irqs) {

			at91_aic_write(AT91_AIC5_SSR,

				       bit & AT91_AIC5_INTSEL_MSK);

			at91_aic_write(AT91_AIC5_IECR, 1);

			i = bit;

		}

	} else {

		at91_aic_write(AT91_AIC_IDCR, *backups);
@@ -118,23 +116,21 @@ void at91_irq_suspend(void) 


void at91_irq_resume(void)

{

	int i = 0, bit;

	int bit = -1;



	if (has_aic5()) {

		/* disable wakeup irqs */

		while ((bit = find_next_bit(wakeups, n_irqs, i)) < n_irqs) {

		while ((bit = find_next_bit(wakeups, n_irqs, bit + 1)) < n_irqs) {

			at91_aic_write(AT91_AIC5_SSR,

				       bit & AT91_AIC5_INTSEL_MSK);

			at91_aic_write(AT91_AIC5_IDCR, 1);

			i = bit;

		}

		/* enable irqs disabled for suspend */

		i = 0;

		while ((bit = find_next_bit(backups, n_irqs, i)) < n_irqs) {

		bit = -1;

		while ((bit = find_next_bit(backups, n_irqs, bit + 1)) < n_irqs) {

			at91_aic_write(AT91_AIC5_SSR,

				       bit & AT91_AIC5_INTSEL_MSK);

			at91_aic_write(AT91_AIC5_IECR, 1);

			i = bit;

		}

	} else {

		at91_aic_write(AT91_AIC_IDCR, *wakeups);