Commit 0e7a16f9 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/wm: add .get_hw_state to watermark funcs 



Get rid of the if ladder in intel_modeset_setup_hw_state() and hide a
number of functions by adding a .get_hw_state() hook to watermark
functions. At least for now, combine the platform specific sanitization
to the hw state readouts on the relevant platforms instead of adding a
separate hook for that.

There's a functional change on PCH split platforms: If i9xx_wm_init()
fails to read plane latency and chooses the nop functions,
ilk_wm_get_hw_state() won't get called for readout. Add the
ilk_init_lp_watermarks() call on that path which now won't be called in
.get_hw_state(), as it looks like the only thing that could make a
difference.

v2:
- Add missing static (kernel test robot)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/6da32831e40606cc8b90491b83196917f2ce36ab.1676317696.git.jani.nikula@intel.com
parent 284c5baa

drivers/gpu/drm/i915/display/i9xx_wm.c

+21 −5
Original line number Diff line number Diff line
@@ -3487,7 +3487,7 @@ static void vlv_read_wm_values(struct drm_i915_private *dev_priv, 
#undef _FW_WM

#undef _FW_WM_VLV



void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv)

static void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv)

{

	struct g4x_wm_values *wm = &dev_priv->display.wm.g4x;

	struct intel_crtc *crtc;
@@ -3580,7 +3580,7 @@ void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv) 
		    str_yes_no(wm->fbc_en));

}



void g4x_wm_sanitize(struct drm_i915_private *dev_priv)

static void g4x_wm_sanitize(struct drm_i915_private *dev_priv)

{

	struct intel_plane *plane;

	struct intel_crtc *crtc;
@@ -3629,7 +3629,13 @@ void g4x_wm_sanitize(struct drm_i915_private *dev_priv) 
	mutex_unlock(&dev_priv->display.wm.wm_mutex);

}



void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv)

static void g4x_wm_get_hw_state_and_sanitize(struct drm_i915_private *i915)

{

	g4x_wm_get_hw_state(i915);

	g4x_wm_sanitize(i915);

}



static void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv)

{

	struct vlv_wm_values *wm = &dev_priv->display.wm.vlv;

	struct intel_crtc *crtc;
@@ -3729,7 +3735,7 @@ void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv) 
		    wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);

}



void vlv_wm_sanitize(struct drm_i915_private *dev_priv)

static void vlv_wm_sanitize(struct drm_i915_private *dev_priv)

{

	struct intel_plane *plane;

	struct intel_crtc *crtc;
@@ -3775,6 +3781,12 @@ void vlv_wm_sanitize(struct drm_i915_private *dev_priv) 
	mutex_unlock(&dev_priv->display.wm.wm_mutex);

}



static void vlv_wm_get_hw_state_and_sanitize(struct drm_i915_private *i915)

{

	vlv_wm_get_hw_state(i915);

	vlv_wm_sanitize(i915);

}



/*

 * FIXME should probably kill this and improve

 * the real watermark readout/sanitation instead
@@ -3791,7 +3803,7 @@ static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv) 
	 */

}



void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv)

static void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv)

{

	struct ilk_wm_values *hw = &dev_priv->display.wm.hw;

	struct intel_crtc *crtc;
@@ -3829,6 +3841,7 @@ static const struct intel_wm_funcs ilk_wm_funcs = { 
	.compute_intermediate_wm = ilk_compute_intermediate_wm,

	.initial_watermarks = ilk_initial_watermarks,

	.optimize_watermarks = ilk_optimize_watermarks,

	.get_hw_state = ilk_wm_get_hw_state,

};



static const struct intel_wm_funcs vlv_wm_funcs = {
@@ -3837,6 +3850,7 @@ static const struct intel_wm_funcs vlv_wm_funcs = { 
	.initial_watermarks = vlv_initial_watermarks,

	.optimize_watermarks = vlv_optimize_watermarks,

	.atomic_update_watermarks = vlv_atomic_update_fifo,

	.get_hw_state = vlv_wm_get_hw_state_and_sanitize,

};



static const struct intel_wm_funcs g4x_wm_funcs = {
@@ -3844,6 +3858,7 @@ static const struct intel_wm_funcs g4x_wm_funcs = { 
	.compute_intermediate_wm = g4x_compute_intermediate_wm,

	.initial_watermarks = g4x_initial_watermarks,

	.optimize_watermarks = g4x_optimize_watermarks,

	.get_hw_state = g4x_wm_get_hw_state_and_sanitize,

};



static const struct intel_wm_funcs pnv_wm_funcs = {
@@ -3877,6 +3892,7 @@ void i9xx_wm_init(struct drm_i915_private *dev_priv) 
		     dev_priv->display.wm.spr_latency[0] && dev_priv->display.wm.cur_latency[0])) {

			dev_priv->display.funcs.wm = &ilk_wm_funcs;

		} else {

			ilk_init_lp_watermarks(dev_priv);

			drm_dbg_kms(&dev_priv->drm,

				    "Failed to read display plane latency. "

				    "Disable CxSR\n");

drivers/gpu/drm/i915/display/i9xx_wm.h

+0 −5
Original line number Diff line number Diff line
@@ -13,11 +13,6 @@ struct intel_crtc_state; 
struct intel_plane_state;



int ilk_wm_max_level(const struct drm_i915_private *i915);

void g4x_wm_get_hw_state(struct drm_i915_private *i915);

void vlv_wm_get_hw_state(struct drm_i915_private *i915);

void ilk_wm_get_hw_state(struct drm_i915_private *i915);

void g4x_wm_sanitize(struct drm_i915_private *i915);

void vlv_wm_sanitize(struct drm_i915_private *i915);

bool ilk_disable_lp_wm(struct drm_i915_private *i915);

bool intel_set_memory_cxsr(struct drm_i915_private *i915, bool enable);

void i9xx_wm_init(struct drm_i915_private *i915);

drivers/gpu/drm/i915/display/intel_display_core.h

+1 −0
Original line number Diff line number Diff line
@@ -85,6 +85,7 @@ struct intel_wm_funcs { 
	void (*optimize_watermarks)(struct intel_atomic_state *state,

				    struct intel_crtc *crtc);

	int (*compute_global_watermarks)(struct intel_atomic_state *state);

	void (*get_hw_state)(struct drm_i915_private *i915);

};



struct intel_audio_state {

drivers/gpu/drm/i915/display/intel_modeset_setup.c

+2 −12
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 
#include "intel_modeset_setup.h"

#include "intel_pch_display.h"

#include "intel_pm.h"

#include "intel_wm.h"

#include "skl_watermark.h"



static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
@@ -724,18 +725,7 @@ void intel_modeset_setup_hw_state(struct drm_i915_private *i915, 


	intel_dpll_sanitize_state(i915);



	if (IS_G4X(i915)) {

		g4x_wm_get_hw_state(i915);

		g4x_wm_sanitize(i915);

	} else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {

		vlv_wm_get_hw_state(i915);

		vlv_wm_sanitize(i915);

	} else if (DISPLAY_VER(i915) >= 9) {

		skl_wm_get_hw_state(i915);

		skl_wm_sanitize(i915);

	} else if (HAS_PCH_SPLIT(i915)) {

		ilk_wm_get_hw_state(i915);

	}

	intel_wm_get_hw_state(i915);



	for_each_intel_crtc(&i915->drm, crtc) {

		struct intel_crtc_state *crtc_state =

drivers/gpu/drm/i915/display/intel_wm.c

+6 −0
Original line number Diff line number Diff line
@@ -114,6 +114,12 @@ int intel_compute_global_watermarks(struct intel_atomic_state *state) 
	return 0;

}



void intel_wm_get_hw_state(struct drm_i915_private *i915)

{

	if (i915->display.funcs.wm->get_hw_state)

		return i915->display.funcs.wm->get_hw_state(i915);

}



bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,

			    const struct intel_plane_state *plane_state)

{