Commit 0e5d5ae8 authored by D Scott Phillips's avatar D Scott Phillips Committed by Catalin Marinas
Browse files

arm64: Add AMPERE1 to the Spectre-BHB affected list 



Per AmpereOne erratum AC03_CPU_12, "Branch history may allow control of
speculative execution across software contexts," the AMPERE1 core needs the
bhb clearing loop to mitigate Spectre-BHB, with a loop iteration count of
11.

Signed-off-by: default avatarD Scott Phillips <scott@os.amperecomputing.com>
Link: https://lore.kernel.org/r/20221011022140.432370-1-scott@os.amperecomputing.com


Reviewed-by: default avatarJames Morse <james.morse@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent a8e5e514

arch/arm64/include/asm/cputype.h

+4 −0
Original line number Diff line number Diff line
@@ -60,6 +60,7 @@ 
#define ARM_CPU_IMP_FUJITSU		0x46

#define ARM_CPU_IMP_HISI		0x48

#define ARM_CPU_IMP_APPLE		0x61

#define ARM_CPU_IMP_AMPERE		0xC0



#define ARM_CPU_PART_AEM_V8		0xD0F

#define ARM_CPU_PART_FOUNDATION		0xD00
@@ -123,6 +124,8 @@ 
#define APPLE_CPU_PART_M1_ICESTORM_MAX	0x028

#define APPLE_CPU_PART_M1_FIRESTORM_MAX	0x029



#define AMPERE_CPU_PART_AMPERE1		0xAC3



#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)

#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)

#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
@@ -172,6 +175,7 @@ 
#define MIDR_APPLE_M1_FIRESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_PRO)

#define MIDR_APPLE_M1_ICESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_MAX)

#define MIDR_APPLE_M1_FIRESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_MAX)

#define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)



/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */

#define MIDR_FUJITSU_ERRATUM_010001		MIDR_FUJITSU_A64FX

arch/arm64/kernel/proton-pack.c

+6 −0
Original line number Diff line number Diff line
@@ -868,6 +868,10 @@ u8 spectre_bhb_loop_affected(int scope) 
			MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),

			{},

		};

		static const struct midr_range spectre_bhb_k11_list[] = {

			MIDR_ALL_VERSIONS(MIDR_AMPERE1),

			{},

		};

		static const struct midr_range spectre_bhb_k8_list[] = {

			MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),

			MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
@@ -878,6 +882,8 @@ u8 spectre_bhb_loop_affected(int scope) 
			k = 32;

		else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k24_list))

			k = 24;

		else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k11_list))

			k = 11;

		else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k8_list))

			k =  8;