Commit 0de5ec44 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'spi-fix-v6.5-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi 

Pull spi fixes from Mark Brown:
 "A couple more small driver specific fixes for v6.5.

  The device mode for Cadence had been broken by some recent updates
  done for host mode and large transfers for multi-byte words on stm32
  had been broken by an API update in what I think was a rebasing
  incident"

* tag 'spi-fix-v6.5-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
  spi: spi-cadence: Fix data corruption issues in slave mode
  spi: stm32: fix accidential revert to byte-sized transfer splitting
parents b5cc3833 627d05a4

drivers/spi/spi-cadence.c

+12 −7
Original line number Diff line number Diff line
@@ -317,12 +317,6 @@ static void cdns_spi_process_fifo(struct cdns_spi *xspi, int ntx, int nrx) 
	xspi->rx_bytes -= nrx;



	while (ntx || nrx) {

		/* When xspi in busy condition, bytes may send failed,

		 * then spi control did't work thoroughly, add one byte delay

		 */

		if (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_TXFULL)

			udelay(10);



		if (ntx) {

			if (xspi->txbuf)

				cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++);
@@ -392,6 +386,11 @@ static irqreturn_t cdns_spi_irq(int irq, void *dev_id) 
		if (xspi->tx_bytes) {

			cdns_spi_process_fifo(xspi, trans_cnt, trans_cnt);

		} else {

			/* Fixed delay due to controller limitation with

			 * RX_NEMPTY incorrect status

			 * Xilinx AR:65885 contains more details

			 */

			udelay(10);

			cdns_spi_process_fifo(xspi, 0, trans_cnt);

			cdns_spi_write(xspi, CDNS_SPI_IDR,

				       CDNS_SPI_IXR_DEFAULT);
@@ -439,12 +438,18 @@ static int cdns_transfer_one(struct spi_controller *ctlr, 
		cdns_spi_setup_transfer(spi, transfer);

	} else {

		/* Set TX empty threshold to half of FIFO depth

		 * only if TX bytes are more than half FIFO depth.

		 * only if TX bytes are more than FIFO depth.

		 */

		if (xspi->tx_bytes > xspi->tx_fifo_depth)

			cdns_spi_write(xspi, CDNS_SPI_THLD, xspi->tx_fifo_depth >> 1);

	}



	/* When xspi in busy condition, bytes may send failed,

	 * then spi control didn't work thoroughly, add one byte delay

	 */

	if (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_TXFULL)

		udelay(10);



	cdns_spi_process_fifo(xspi, xspi->tx_fifo_depth, 0);

	spi_transfer_delay_exec(transfer);

drivers/spi/spi-stm32.c

+3 −3
Original line number Diff line number Diff line
@@ -1001,7 +1001,7 @@ static int stm32_spi_prepare_msg(struct spi_controller *ctrl, 
	if (spi->cfg->set_number_of_data) {

		int ret;



		ret = spi_split_transfers_maxsize(ctrl, msg,

		ret = spi_split_transfers_maxwords(ctrl, msg,

						   STM32H7_SPI_TSIZE_MAX,

						   GFP_KERNEL | GFP_DMA);

		if (ret)