Commit 0dd79532 authored by Zhan Liu's avatar Zhan Liu Committed by Alex Deucher
Browse files

drm/amdgpu/display: Implement functions to let DC allocate GPU memory



[Why]
DC needs to communicate with PM FW through GPU memory. In order
to do so we need to be able to allocate memory from within DC.

[How]
Call amdgpu_bo_create_kernel to allocate GPU memory and use a
list in amdgpu_display_manager to track our allocations so we
can clean them up later.

Signed-off-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarZhan Liu <zhan.liu@amd.com>
Reviewed-by: default avatarCharlene Liu <charlene.liu@amd.com>
Acked-by: default avatarZhan Liu <zhan.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 89551f23
Loading
Loading
Loading
Loading
+1 −0
Original line number Diff line number Diff line
@@ -1086,6 +1086,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)

	init_data.flags.power_down_display_on_boot = true;

	INIT_LIST_HEAD(&adev->dm.da_list);
	/* Display Core create. */
	adev->dm.dc = dc_create(&init_data);

+16 −0
Original line number Diff line number Diff line
@@ -132,6 +132,16 @@ struct amdgpu_dm_backlight_caps {
	bool aux_support;
};

/**
 * struct dal_allocation - Tracks mapped FB memory for SMU communication
 */
struct dal_allocation {
	struct list_head list;
	struct amdgpu_bo *bo;
	void *cpu_ptr;
	u64 gpu_addr;
};

/**
 * struct amdgpu_display_manager - Central amdgpu display manager device
 *
@@ -385,6 +395,12 @@ struct amdgpu_display_manager {
	 */
	struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC];
	bool force_timing_sync;
	/**
	 * @da_list:
	 *
	 * DAL fb memory allocation list, for communication with SMU.
	 */
	struct list_head da_list;
};

enum dsc_clock_force_state {
+37 −3
Original line number Diff line number Diff line
@@ -652,16 +652,50 @@ void *dm_helpers_allocate_gpu_mem(
		size_t size,
		long long *addr)
{
	// TODO
	struct amdgpu_device *adev = ctx->driver_context;
	struct dal_allocation *da;
	u32 domain = (type == DC_MEM_ALLOC_TYPE_GART) ?
		AMDGPU_GEM_DOMAIN_GTT : AMDGPU_GEM_DOMAIN_VRAM;
	int ret;

	da = kzalloc(sizeof(struct dal_allocation), GFP_KERNEL);
	if (!da)
		return NULL;

	ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
				      domain, &da->bo,
				      &da->gpu_addr, &da->cpu_ptr);

	*addr = da->gpu_addr;

	if (ret) {
		kfree(da);
		return NULL;
	}

	/* add da to list in dm */
	list_add(&da->list, &adev->dm.da_list);

	return da->cpu_ptr;
}

void dm_helpers_free_gpu_mem(
		struct dc_context *ctx,
		enum dc_gpu_mem_alloc_type type,
		void *pvMem)
{
	// TODO
	struct amdgpu_device *adev = ctx->driver_context;
	struct dal_allocation *da;

	/* walk the da list in DM */
	list_for_each_entry(da, &adev->dm.da_list, list) {
		if (pvMem == da->cpu_ptr) {
			amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr);
			list_del(&da->list);
			kfree(da);
			break;
		}
	}
}

bool dm_helpes_dmub_outbox0_interrupt_control(struct dc_context *ctx, bool enable)