Unverified Commit 0d98fbcf authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'socfpga_updates_for_v5.20_part2' of...

Merge tag 'socfpga_updates_for_v5.20_part2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/late

SoCFPGA dts updates for v5.20, part 2
- Update EMAC AXI settings for Cyclone5

* tag 'socfpga_updates_for_v5.20_part2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  ARM: dts: add EMAC AXI settings for Cyclone5
  arm64: dts: altera: socfpga_stratix10: move clocks out of soc node
  arm64: dts: Add support for Stratix 10 Software Virtual Platform
  dt-bindings: altera: document Stratix 10 SWVP compatibles
  arm64: dts: altera: adjust whitespace around '='
  arm64: dts: intel: socfpga_agilex: use defined GIC interrupt type for ECC
  dt-bindings: altera: Add Chameleon v3 board
  ARM: dts: socfpga: Add Google Chameleon v3 devicetree
  ARM: dts: socfpga: Add atsha204a node to Mercury+ AA1 dts
  ARM: dts: socfpga: Move sdmmc-ecc node to Arria 10 dts
  ARM: dts: socfpga: Change Mercury+ AA1 dts to dtsi

Link: https://lore.kernel.org/r/20220728223237.3184243-1-dinguyen@kernel.org


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 87df0cec b3cbbb58
Loading
Loading
Loading
Loading
+9 −1
Original line number Diff line number Diff line
@@ -25,7 +25,14 @@ properties:
        items:
          - enum:
              - altr,socfpga-arria10-socdk
              - enclustra,mercury-aa1
          - const: altr,socfpga-arria10
          - const: altr,socfpga

      - description: Mercury+ AA1 boards
        items:
          - enum:
              - google,chameleon-v3
          - const: enclustra,mercury-aa1
          - const: altr,socfpga-arria10
          - const: altr,socfpga

@@ -47,6 +54,7 @@ properties:
        items:
          - enum:
              - altr,socfpga-stratix10-socdk
              - altr,socfpga-stratix10-swvp
          - const: altr,socfpga-stratix10

      - description: SoCFPGA VT
+1 −1
Original line number Diff line number Diff line
@@ -1148,7 +1148,7 @@ dtb-$(CONFIG_ARCH_S5PV210) += \
	s5pv210-torbreck.dtb
dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \
	socfpga_arria5_socdk.dtb \
	socfpga_arria10_mercury_aa1.dtb \
	socfpga_arria10_chameleonv3.dtb \
	socfpga_arria10_socdk_nand.dtb \
	socfpga_arria10_socdk_qspi.dtb \
	socfpga_arria10_socdk_sdmmc.dtb \
+8 −0
Original line number Diff line number Diff line
@@ -561,6 +561,12 @@
			interrupts = <0 175 4>;
		};

		socfpga_axi_setup: stmmac-axi-config {
			snps,wr_osr_lmt = <0xf>;
			snps,rd_osr_lmt = <0xf>;
			snps,blen = <0 0 0 0 16 0 0>;
		};

		gmac0: ethernet@ff700000 {
			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
			altr,sysmgr-syscon = <&sysmgr 0x60 0>;
@@ -576,6 +582,7 @@
			snps,perfect-filter-entries = <128>;
			tx-fifo-depth = <4096>;
			rx-fifo-depth = <4096>;
			snps,axi-config = <&socfpga_axi_setup>;
			status = "disabled";
		};

@@ -594,6 +601,7 @@
			snps,perfect-filter-entries = <128>;
			tx-fifo-depth = <4096>;
			rx-fifo-depth = <4096>;
			snps,axi-config = <&socfpga_axi_setup>;
			status = "disabled";
		};

+10 −0
Original line number Diff line number Diff line
@@ -736,6 +736,16 @@
					     <37 IRQ_TYPE_LEVEL_HIGH>;
			};

			sdmmca-ecc@ff8c2c00 {
				compatible = "altr,socfpga-sdmmc-ecc";
				reg = <0xff8c2c00 0x400>;
				altr,ecc-parent = <&mmc>;
				interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
					     <47 IRQ_TYPE_LEVEL_HIGH>,
					     <16 IRQ_TYPE_LEVEL_HIGH>,
					     <48 IRQ_TYPE_LEVEL_HIGH>;
			};

			dma-ecc@ff8c8000 {
				compatible = "altr,socfpga-dma-ecc";
				reg = <0xff8c8000 0x400>;
+90 −0
Original line number Diff line number Diff line
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright 2022 Google LLC
 */
/dts-v1/;
#include "socfpga_arria10_mercury_aa1.dtsi"

/ {
	model = "Google Chameleon V3";
	compatible = "google,chameleon-v3", "enclustra,mercury-aa1",
		     "altr,socfpga-arria10", "altr,socfpga";

	aliases {
		serial0 = &uart0;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
	};
};

&gmac0 {
	status = "okay";
};

&gpio0 {
	status = "okay";
};

&gpio1 {
	status = "okay";
};

&gpio2 {
	status = "okay";
};

&i2c0 {
	status = "okay";

	ssm2603: audio-codec@1a {
		compatible = "adi,ssm2603";
		reg = <0x1a>;
	};
};

&i2c1 {
	status = "okay";

	u80: gpio@21 {
		compatible = "nxp,pca9535";
		reg = <0x21>;
		gpio-controller;
		#gpio-cells = <2>;

		gpio-line-names =
			"SOM_AUD_MUTE",
			"DP1_OUT_CEC_EN",
			"DP2_OUT_CEC_EN",
			"DP1_SOM_PS8469_CAD",
			"DPD_SOM_PS8469_CAD",
			"DP_OUT_PWR_EN",
			"STM32_RST_L",
			"STM32_BOOT0",

			"FPGA_PROT",
			"STM32_FPGA_COMM0",
			"TP119",
			"TP120",
			"TP121",
			"TP122",
			"TP123",
			"TP124";
	};
};

&mmc {
	status = "okay";
};

&uart0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&usb0 {
	status = "okay";
	dr_mode = "host";
};
Loading