Commit 0d31441e authored by Danielle Ratson's avatar Danielle Ratson Committed by David S. Miller
Browse files

mlxsw: reg: Add Port Module Type Mapping register 



Add the Port Module Type Mapping (PMTP) register. It will be used by
subsequent patches to query port module types and forbid certain
configurations based on the port module's type.

Signed-off-by: default avatarDanielle Ratson <danieller@nvidia.com>
Signed-off-by: default avatarIdo Schimmel <idosch@nvidia.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 78cf4b92

drivers/net/ethernet/mellanox/mlxsw/reg.h

+53 −0
Original line number Diff line number Diff line
@@ -6064,6 +6064,58 @@ static inline void mlxsw_reg_pllp_unpack(char *payload, u8 *label_port, 
	*slot_index = mlxsw_reg_pllp_slot_index_get(payload);

}



/* PMTM - Port Module Type Mapping Register

 * ----------------------------------------

 * The PMTM register allows query or configuration of module types.

 * The register can only be set when the module is disabled by PMAOS register

 */

#define MLXSW_REG_PMTM_ID 0x5067

#define MLXSW_REG_PMTM_LEN 0x10



MLXSW_REG_DEFINE(pmtm, MLXSW_REG_PMTM_ID, MLXSW_REG_PMTM_LEN);



/* reg_pmtm_slot_index

 * Slot index.

 * Access: Index

 */

MLXSW_ITEM32(reg, pmtm, slot_index, 0x00, 24, 4);



/* reg_pmtm_module

 * Module number.

 * Access: Index

 */

MLXSW_ITEM32(reg, pmtm, module, 0x00, 16, 8);



enum mlxsw_reg_pmtm_module_type {

	MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_4_LANES = 0,

	MLXSW_REG_PMTM_MODULE_TYPE_QSFP = 1,

	MLXSW_REG_PMTM_MODULE_TYPE_SFP = 2,

	MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_SINGLE_LANE = 4,

	MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_2_LANES = 8,

	MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP4X = 10,

	MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP2X = 11,

	MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP1X = 12,

	MLXSW_REG_PMTM_MODULE_TYPE_QSFP_DD = 14,

	MLXSW_REG_PMTM_MODULE_TYPE_OSFP = 15,

	MLXSW_REG_PMTM_MODULE_TYPE_SFP_DD = 16,

	MLXSW_REG_PMTM_MODULE_TYPE_DSFP = 17,

	MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP8X = 18,

	MLXSW_REG_PMTM_MODULE_TYPE_TWISTED_PAIR = 19,

};



/* reg_pmtm_module_type

 * Module type.

 * Access: RW

 */

MLXSW_ITEM32(reg, pmtm, module_type, 0x04, 0, 5);



static inline void mlxsw_reg_pmtm_pack(char *payload, u8 slot_index, u8 module)

{

	MLXSW_REG_ZERO(pmtm, payload);

	mlxsw_reg_pmtm_slot_index_set(payload, slot_index);

	mlxsw_reg_pmtm_module_set(payload, module);

}



/* HTGT - Host Trap Group Table

 * ----------------------------

 * Configures the properties for forwarding to CPU.
@@ -12570,6 +12622,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 
	MLXSW_REG(pddr),

	MLXSW_REG(pmmp),

	MLXSW_REG(pllp),

	MLXSW_REG(pmtm),

	MLXSW_REG(htgt),

	MLXSW_REG(hpkt),

	MLXSW_REG(rgcr),