Commit 0d2f2cef authored by Garmin.Chang's avatar Garmin.Chang Committed by Stephen Boyd
Browse files

clk: mediatek: Add MT8188 adsp clock support 



Add MT8188 adsp clock controller which provides clock gate
control for Audio DSP.

Signed-off-by: default avatarGarmin.Chang <Garmin.Chang@mediatek.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230331123621.16167-20-Garmin.Chang@mediatek.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 1b5e5299

drivers/clk/mediatek/Kconfig

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@@ -692,6 +692,13 @@ config COMMON_CLK_MT8188 
	help

          This driver supports MediaTek MT8188 clocks.



config COMMON_CLK_MT8188_ADSP_AUDIO26M

	tristate "Clock driver for MediaTek MT8188 adsp audio26m"

	depends on COMMON_CLK_MT8188

	default COMMON_CLK_MT8188

	help

	  This driver supports MediaTek MT8188 adsp audio26m clocks.



config COMMON_CLK_MT8188_CAMSYS

	tristate "Clock driver for MediaTek MT8188 camsys"

	depends on COMMON_CLK_MT8188_VPPSYS

drivers/clk/mediatek/Makefile

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@@ -102,6 +102,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186_VENCSYS) += clk-mt8186-venc.o 
obj-$(CONFIG_COMMON_CLK_MT8186_WPESYS) += clk-mt8186-wpe.o

obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o \

				   clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o

obj-$(CONFIG_COMMON_CLK_MT8188_ADSP_AUDIO26M) += clk-mt8188-adsp_audio26m.o

obj-$(CONFIG_COMMON_CLK_MT8188_CAMSYS) += clk-mt8188-cam.o clk-mt8188-ccu.o

obj-$(CONFIG_COMMON_CLK_MT8188_IMGSYS) += clk-mt8188-img.o

obj-$(CONFIG_COMMON_CLK_MT8188_IMP_IIC_WRAP) += clk-mt8188-imp_iic_wrap.o

drivers/clk/mediatek/clk-mt8188-adsp_audio26m.c

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// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2022 MediaTek Inc.

 * Author: Garmin Chang <garmin.chang@mediatek.com>

 */



#include <dt-bindings/clock/mediatek,mt8188-clk.h>

#include <linux/clk-provider.h>

#include <linux/platform_device.h>



#include "clk-gate.h"

#include "clk-mtk.h"



static const struct mtk_gate_regs adsp_audio26m_cg_regs = {

	.set_ofs = 0x80,

	.clr_ofs = 0x80,

	.sta_ofs = 0x80,

};



#define GATE_ADSP_FLAGS(_id, _name, _parent, _shift)		\

	GATE_MTK(_id, _name, _parent, &adsp_audio26m_cg_regs, _shift,		\

		&mtk_clk_gate_ops_no_setclr)



static const struct mtk_gate adsp_audio26m_clks[] = {

	GATE_ADSP_FLAGS(CLK_AUDIODSP_AUDIO26M, "audiodsp_audio26m", "clk26m", 3),

};



static const struct mtk_clk_desc adsp_audio26m_desc = {

	.clks = adsp_audio26m_clks,

	.num_clks = ARRAY_SIZE(adsp_audio26m_clks),

};



static const struct of_device_id of_match_clk_mt8188_adsp_audio26m[] = {

	{ .compatible = "mediatek,mt8188-adsp-audio26m", .data = &adsp_audio26m_desc },

	{ /* sentinel */ }

};

MODULE_DEVICE_TABLE(platform, of_match_clk_mt8188_adsp_audio26m);



static struct platform_driver clk_mt8188_adsp_audio26m_drv = {

	.probe = mtk_clk_simple_probe,

	.remove = mtk_clk_simple_remove,

	.driver = {

		.name = "clk-mt8188-adsp_audio26m",

		.of_match_table = of_match_clk_mt8188_adsp_audio26m,

	},

};

module_platform_driver(clk_mt8188_adsp_audio26m_drv);

MODULE_LICENSE("GPL");