Unverified Commit 0d2b96af authored by Maxime Ripard's avatar Maxime Ripard
Browse files

drm/vc4: crtc: Clear the PixelValve FIFO on disable 



In order to avoid a stale pixel getting stuck on mode change or a disable
/ enable cycle, we need to make sure to flush the PV FIFO on disable.

Signed-off-by: default avatarMaxime Ripard <maxime@cerno.tech>
Tested-by: default avatarChanwoo Choi <cw00.choi@samsung.com>
Tested-by: default avatarHoegeun Kwon <hoegeun.kwon@samsung.com>
Tested-by: default avatarStefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: default avatarDave Stevenson <dave.stevenson@raspberrypi.com>
Link: https://patchwork.freedesktop.org/patch/msgid/26fe48b09d77088679ed0c8cb8cf0db2f108195e.1599120059.git-series.maxime@cerno.tech
parent b7cb67a6

drivers/gpu/drm/vc4/vc4_crtc.c

+1 −2
Original line number Diff line number Diff line
@@ -424,8 +424,7 @@ static void vc4_crtc_atomic_disable(struct drm_crtc *crtc, 
	if (vc4_encoder->post_crtc_disable)

		vc4_encoder->post_crtc_disable(encoder);



	CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) & ~PV_CONTROL_EN);



	vc4_crtc_pixelvalve_reset(crtc);

	vc4_hvs_atomic_disable(crtc, old_state);



	if (vc4_encoder->post_crtc_powerdown)