PCI: qcom: Add IPQ60xx support (0cf7c2ef) · Commits · EulixOS / Software / Kernel

drivers/pci/controller/dwc/pcie-designware.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -76,6 +76,7 @@

		#define GEN3_RELATED_OFF 0x890
		#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0)
		#define GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS BIT(13)
		#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)
		#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
		#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)

drivers/pci/controller/dwc/pcie-qcom.c

+130 −0

Original line number	Diff line number	Diff line
		@@ -52,6 +52,10 @@
		#define PCIE20_PARF_DBI_BASE_ADDR 0x168
		#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C
		#define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174
		#define AHB_CLK_EN BIT(0)
		#define MSTR_AXI_CLK_EN BIT(1)
		#define BYPASS BIT(4)

		#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178
		#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8
		#define PCIE20_PARF_LTSSM 0x1B0
		@@ -179,6 +183,11 @@ struct qcom_pcie_resources_2_7_0 {
		struct reset_control *pci_reset;
		};

		struct qcom_pcie_resources_2_9_0 {
		struct clk_bulk_data clks[5];
		struct reset_control *rst;
		};

		union qcom_pcie_resources {
		struct qcom_pcie_resources_1_0_0 v1_0_0;
		struct qcom_pcie_resources_2_1_0 v2_1_0;
		@@ -186,6 +195,7 @@ union qcom_pcie_resources {
		struct qcom_pcie_resources_2_3_3 v2_3_3;
		struct qcom_pcie_resources_2_4_0 v2_4_0;
		struct qcom_pcie_resources_2_7_0 v2_7_0;
		struct qcom_pcie_resources_2_9_0 v2_9_0;
		};

		struct qcom_pcie;
		@@ -1279,6 +1289,112 @@ static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie)
		regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
		}

		static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie)
		{
		struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
		struct dw_pcie *pci = pcie->pci;
		struct device *dev = pci->dev;
		int ret;

		res->clks[0].id = "iface";
		res->clks[1].id = "axi_m";
		res->clks[2].id = "axi_s";
		res->clks[3].id = "axi_bridge";
		res->clks[4].id = "rchng";

		ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
		if (ret < 0)
		return ret;

		res->rst = devm_reset_control_array_get_exclusive(dev);
		if (IS_ERR(res->rst))
		return PTR_ERR(res->rst);

		return 0;
		}

		static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie)
		{
		struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;

		clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
		}

		static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie)
		{
		struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
		struct device *dev = pcie->pci->dev;
		int ret;

		ret = reset_control_assert(res->rst);
		if (ret) {
		dev_err(dev, "reset assert failed (%d)\n", ret);
		return ret;
		}

		/*
		* Delay periods before and after reset deassert are working values
		* from downstream Codeaurora kernel
		*/
		usleep_range(2000, 2500);

		ret = reset_control_deassert(res->rst);
		if (ret) {
		dev_err(dev, "reset deassert failed (%d)\n", ret);
		return ret;
		}

		usleep_range(2000, 2500);

		return clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
		}

		static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
		{
		struct dw_pcie *pci = pcie->pci;
		u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
		u32 val;
		int i;

		writel(SLV_ADDR_SPACE_SZ,
		pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);

		val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
		val &= ~BIT(0);
		writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);

		writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);

		writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
		writel(BYPASS \| MSTR_AXI_CLK_EN \| AHB_CLK_EN,
		pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
		writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS \|
		GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL,
		pci->dbi_base + GEN3_RELATED_OFF);

		writel(MST_WAKEUP_EN \| SLV_WAKEUP_EN \| MSTR_ACLK_CGC_DIS \|
		SLV_ACLK_CGC_DIS \| CORE_CLK_CGC_DIS \|
		AUX_PWR_DET \| L23_CLK_RMV_DIS \| L1_CLK_RMV_DIS,
		pcie->parf + PCIE20_PARF_SYS_CTRL);

		writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);

		dw_pcie_dbi_ro_wr_en(pci);
		writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);

		val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
		val &= ~PCI_EXP_LNKCAP_ASPMS;
		writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);

		writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
		PCI_EXP_DEVCTL2);

		for (i = 0; i < 256; i++)
		writel(0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N + (4 * i));

		return 0;
		}

		static int qcom_pcie_link_up(struct dw_pcie *pci)
		{
		u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
		@@ -1468,6 +1584,15 @@ static const struct qcom_pcie_ops ops_1_9_0 = {
		.config_sid = qcom_pcie_config_sid_sm8250,
		};

		/* Qcom IP rev.: 2.9.0 Synopsys IP rev.: 5.00a */
		static const struct qcom_pcie_ops ops_2_9_0 = {
		.get_resources = qcom_pcie_get_resources_2_9_0,
		.init = qcom_pcie_init_2_9_0,
		.post_init = qcom_pcie_post_init_2_9_0,
		.deinit = qcom_pcie_deinit_2_9_0,
		.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
		};

		static const struct qcom_pcie_cfg apq8084_cfg = {
		.ops = &ops_1_0_0,
		};
		@@ -1529,6 +1654,10 @@ static const struct qcom_pcie_cfg sc8180x_cfg = {
		.has_tbu_clk = true,
		};

		static const struct qcom_pcie_cfg ipq6018_cfg = {
		.ops = &ops_2_9_0,
		};

		static const struct dw_pcie_ops dw_pcie_ops = {
		.link_up = qcom_pcie_link_up,
		.start_link = qcom_pcie_start_link,
		@@ -1639,6 +1768,7 @@ static const struct of_device_id qcom_pcie_match[] = {
		{ .compatible = "qcom,pcie-sm8450-pcie0", .data = &sm8450_pcie0_cfg },
		{ .compatible = "qcom,pcie-sm8450-pcie1", .data = &sm8450_pcie1_cfg },
		{ .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg },
		{ .compatible = "qcom,pcie-ipq6018", .data = &ipq6018_cfg },
		{ }
		};