Commit 0ce855fd authored by David E. Box's avatar David E. Box Committed by Jun Tian
Browse files

PCI: Add defines for Designated Vendor-Specific Extended Capability 

mainline inclusion
from mainline-v5.11-rc1
commit 1dc2da5c
category: feature
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I596K9


CVE: NA

Intel-SIG: commit 1dc2da5c PCI: Add defines for Designated Vendor-Specific
Extended Capability.
Backport for intel PMT (Platform Monitoring Technology) support
--------------------------------

Add PCIe Designated Vendor-Specific Extended Capability (DVSEC) and defines
for the header offsets. Defined in PCIe r5.0, sec 7.9.6.

Signed-off-by: default avatarDavid E. Box <david.e.box@linux.intel.com>
Acked-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarAndy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: default avatarLee Jones <lee.jones@linaro.org>
Signed-off-by: default avataryingbao jia <yingbao.jia@intel.com>
Signed-off-by: default avatarJun Tian <jun.j.tian@intel.com>
parent dbf4fd06

include/uapi/linux/pci_regs.h

+5 −0
Original line number Original line Diff line number Diff line
@@ -729,6 +729,7 @@ 
#define PCI_EXT_CAP_ID_DPC	0x1D	/* Downstream Port Containment */

#define PCI_EXT_CAP_ID_DPC	0x1D	/* Downstream Port Containment */

#define PCI_EXT_CAP_ID_L1SS	0x1E	/* L1 PM Substates */

#define PCI_EXT_CAP_ID_L1SS	0x1E	/* L1 PM Substates */

#define PCI_EXT_CAP_ID_PTM	0x1F	/* Precision Time Measurement */

#define PCI_EXT_CAP_ID_PTM	0x1F	/* Precision Time Measurement */

#define PCI_EXT_CAP_ID_DVSEC	0x23	/* Designated Vendor-Specific */

#define PCI_EXT_CAP_ID_DLF	0x25	/* Data Link Feature */

#define PCI_EXT_CAP_ID_DLF	0x25	/* Data Link Feature */

#define PCI_EXT_CAP_ID_PL_16GT	0x26	/* Physical Layer 16.0 GT/s */

#define PCI_EXT_CAP_ID_PL_16GT	0x26	/* Physical Layer 16.0 GT/s */

#define PCI_EXT_CAP_ID_MAX	PCI_EXT_CAP_ID_PL_16GT

#define PCI_EXT_CAP_ID_MAX	PCI_EXT_CAP_ID_PL_16GT
@@ -1079,6 +1080,10 @@ 
#define  PCI_L1SS_CTL1_LTR_L12_TH_SCALE	0xe0000000  /* LTR_L1.2_THRESHOLD_Scale */

#define  PCI_L1SS_CTL1_LTR_L12_TH_SCALE	0xe0000000  /* LTR_L1.2_THRESHOLD_Scale */

#define PCI_L1SS_CTL2		0x0c	/* Control 2 Register */

#define PCI_L1SS_CTL2		0x0c	/* Control 2 Register */





/* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */

#define PCI_DVSEC_HEADER1		0x4 /* Designated Vendor-Specific Header1 */

#define PCI_DVSEC_HEADER2		0x8 /* Designated Vendor-Specific Header2 */



/* Data Link Feature */

/* Data Link Feature */

#define PCI_DLF_CAP		0x04	/* Capabilities Register */

#define PCI_DLF_CAP		0x04	/* Capabilities Register */

#define  PCI_DLF_EXCHANGE_ENABLE	0x80000000  /* Data Link Feature Exchange Enable */

#define  PCI_DLF_EXCHANGE_ENABLE	0x80000000  /* Data Link Feature Exchange Enable */