Commit 0cc58f64 authored by Weibo Zhao's avatar Weibo Zhao Committed by JiangShui
Browse files

hns3 udma: add support of query_device_attr 

driver inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I85R2F


CVE: NA

----------------------------------------------------------

Query_device_attr is a function that can query the abilities
of driver and hardware such as max number of jetty.

Signed-off-by: default avatarWeibo Zhao <zhaoweibo3@huawei.com>
parent 203ec155

drivers/ub/hw/hns3/hns3_udma_device.h

+36 −0
Original line number Diff line number Diff line
@@ -65,6 +65,8 @@ 
#define UDMA_TX_CMQ_PI_REG			0x07010

#define UDMA_TX_CMQ_CI_REG			0x07014



#define UDMA_MAX_MSG_LEN			0x80000000



#define UDMA_MAX_BT_REGION			3

#define UDMA_MAX_BT_LEVEL			3
@@ -123,6 +125,11 @@ 
#define UDMA_VF_ABN_INT_EN_REG		0x13008

#define UDMA_VF_EVENT_INT_EN_REG	0x1300c

#define EQ_REG_OFFSET			0x4

#define MTU_VAL_256			256

#define MTU_VAL_512			512

#define MTU_VAL_1024			1024

#define MTU_VAL_2048			2048

#define MTU_VAL_4096			4096

#define UDMA_DEFAULT_MAX_JETTY_X_SHIFT	8



#define UDMA_DB_ADDR_OFFSET 0x230
@@ -188,6 +195,21 @@ enum { 
	TYPE_CSQ = 1

};



enum udma_cong_type {

	UDMA_CONG_TYPE_DCQCN,

	UDMA_CONG_TYPE_LDCP,

	UDMA_CONG_TYPE_HC3,

	UDMA_CONG_TYPE_DIP,

	UDMA_CONG_TYPE_TOTAL,

};



enum udma_cong_sel {

	UDMA_CONG_SEL_DCQCN = 1 << UDMA_CONG_TYPE_DCQCN,

	UDMA_CONG_SEL_LDCP = 1 << UDMA_CONG_TYPE_LDCP,

	UDMA_CONG_SEL_HC3 = 1 << UDMA_CONG_TYPE_HC3,

	UDMA_CONG_SEL_DIP = 1 << UDMA_CONG_TYPE_DIP,

};



enum udma_qp_state {

	QPS_RESET,

	QPS_RTR = 2,
@@ -201,6 +223,20 @@ enum { 
	UDMA_BUF_NOFAIL = BIT(2),

};



static inline enum ubcore_mtu udma_mtu_int_to_enum(int mtu)

{

	if (mtu >= MTU_VAL_4096)

		return UBCORE_MTU_4096;

	else if (mtu >= MTU_VAL_2048)

		return UBCORE_MTU_2048;

	else if (mtu >= MTU_VAL_1024)

		return UBCORE_MTU_1024;

	else if (mtu >= MTU_VAL_512)

		return UBCORE_MTU_512;

	else

		return UBCORE_MTU_256;

}



struct udma_uar {

	uint64_t	pfn;

	uint64_t	index;

drivers/ub/hw/hns3/hns3_udma_main.c

+61 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 
#include <linux/pci.h>

#include "urma/ubcore_api.h"

#include "hns3_udma_abi.h"

#include "hnae3.h"

#include "hns3_udma_device.h"

#include "hns3_udma_hem.h"

#include "hns3_udma_jfr.h"
@@ -189,10 +190,70 @@ static int udma_mmap(struct ubcore_ucontext *uctx, struct vm_area_struct *vma) 


	return 0;

}

static uint16_t query_congest_alg(uint8_t udma_cc_caps)

{

	uint16_t ubcore_cc_alg = 0;



	if (udma_cc_caps & UDMA_CONG_SEL_DCQCN)

		ubcore_cc_alg |= UBCORE_CC_DCQCN;

	if (udma_cc_caps & UDMA_CONG_SEL_LDCP)

		ubcore_cc_alg |= UBCORE_CC_LDCP;

	if (udma_cc_caps & UDMA_CONG_SEL_HC3)

		ubcore_cc_alg |= UBCORE_CC_HC3;

	if (udma_cc_caps & UDMA_CONG_SEL_DIP)

		ubcore_cc_alg |= UBCORE_CC_DIP;



	return ubcore_cc_alg;

}



static int udma_query_device_attr(struct ubcore_device *dev,

				  struct ubcore_device_attr *attr)

{

	struct udma_dev *udma_dev = to_udma_dev(dev);

	struct device *dev_of_udma = udma_dev->dev;

	struct net_device *net_dev;

	int i;



	attr->guid = udma_dev->sys_image_guid;

	attr->dev_cap.max_jfc = (1 << udma_dev->caps.num_jfc_shift);

	attr->dev_cap.max_jfs = (1 << udma_dev->caps.num_jfs_shift);

	attr->dev_cap.max_jfr = (1 << udma_dev->caps.num_jfr_shift);

	attr->dev_cap.max_jetty = (1 << udma_dev->caps.num_jetty_shift);

	attr->dev_cap.max_jfc_depth = udma_dev->caps.max_cqes;

	attr->dev_cap.max_jfs_depth = udma_dev->caps.max_wqes;

	attr->dev_cap.max_jfr_depth = udma_dev->caps.max_srq_wrs;

	attr->dev_cap.max_jfs_inline_size = udma_dev->caps.max_sq_inline;

	attr->dev_cap.max_jfs_sge = udma_dev->caps.max_sq_sg;

	attr->dev_cap.max_jfr_sge = udma_dev->caps.max_srq_sges;

	attr->dev_cap.max_msg_size = UDMA_MAX_MSG_LEN;

	attr->dev_cap.trans_mode = UBCORE_TP_RM | UBCORE_TP_UM;

	attr->dev_cap.feature.bs.oor = udma_dev->caps.oor_en;

	attr->port_cnt = udma_dev->caps.num_ports;

	attr->dev_cap.comp_vector_cnt = udma_dev->caps.num_comp_vectors;

	attr->vf_cnt = udma_dev->func_num - 1;

	attr->dev_cap.feature.bs.jfc_inline = !!(udma_dev->caps.flags & UDMA_CAP_FLAG_CQE_INLINE);

	attr->dev_cap.feature.bs.spray_en = 1;

	attr->dev_cap.max_jfs_rsge = udma_dev->caps.max_sq_sg;

	attr->dev_cap.congestion_ctrl_alg = query_congest_alg(udma_dev->caps.cong_type);



	for (i = 0; i < udma_dev->caps.num_ports; i++) {

		net_dev = udma_dev->uboe.netdevs[i];

		if (!net_dev) {

			dev_err(dev_of_udma, "Find netdev %u failed!\n", i);

			return -EINVAL;

		}

		attr->port_attr[i].max_mtu =

			udma_mtu_int_to_enum(net_dev->max_mtu);

	}



	return 0;

}



static struct ubcore_ops g_udma_dev_ops = {

	.owner = THIS_MODULE,

	.abi_version = 1,

	.set_eid = udma_set_eid,

	.query_device_attr = udma_query_device_attr,

	.alloc_ucontext = udma_alloc_ucontext,

	.free_ucontext = udma_free_ucontext,

	.mmap = udma_mmap,