Unverified Commit 0cb6baf8 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!10219 CVE-2024-35931 

Merge Pull Request from: @ci-robot 
 
PR sync from: Liu Chuang <liuchuang40@huawei.com>
https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/XCT6ZUXS73HZSC3ZA475J3S42V3NZTZY/ 
Fixing CVE-2024-35931

Asad Kamal (1):
  drm/amdgpu : Add hive ras recovery check

Stanley.Yang (1):
  drm/amdgpu: Skip do PCI error slot reset during RAS recovery


-- 
2.34.1
 
https://gitee.com/src-openeuler/kernel/issues/I9QGL7 
 
Link:https://gitee.com/openeuler/kernel/pulls/10219

 

Reviewed-by: default avatarZhang Peng <zhangpeng362@huawei.com>
Signed-off-by: default avatarZhang Peng <zhangpeng362@huawei.com>
parents 0e85cfb0 1b4b1e65

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+14 −0
Original line number Diff line number Diff line
@@ -5742,6 +5742,20 @@ pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev) 
	struct amdgpu_reset_context reset_context;

	u32 memsize;

	struct list_head device_list;

	struct amdgpu_hive_info *hive;

	int hive_ras_recovery = 0;

	struct amdgpu_ras *ras;



	/* PCI error slot reset should be skipped During RAS recovery */

	hive = amdgpu_get_xgmi_hive(adev);

	if (hive) {

		hive_ras_recovery = atomic_read(&hive->ras_recovery);

		amdgpu_put_xgmi_hive(hive);

	}

	ras = amdgpu_ras_get_context(adev);

	if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) &&

		 ras && (atomic_read(&ras->in_recovery) || hive_ras_recovery))

		return PCI_ERS_RESULT_RECOVERED;



	DRM_INFO("PCI error: slot reset callback!!\n");

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

+7 −2
Original line number Diff line number Diff line
@@ -2027,9 +2027,11 @@ static void amdgpu_ras_do_recovery(struct work_struct *work) 
	struct amdgpu_device *remote_adev = NULL;

	struct amdgpu_device *adev = ras->adev;

	struct list_head device_list, *device_list_handle =  NULL;

	struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);



	if (hive)

		atomic_set(&hive->ras_recovery, 1);

	if (!ras->disable_ras_err_cnt_harvest) {

		struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);



		/* Build list of devices to query RAS related errors */

		if  (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
@@ -2046,7 +2048,6 @@ static void amdgpu_ras_do_recovery(struct work_struct *work) 
			amdgpu_ras_log_on_err_counter(remote_adev);

		}



		amdgpu_put_xgmi_hive(hive);

	}



	if (amdgpu_device_should_recover_gpu(ras->adev)) {
@@ -2081,6 +2082,10 @@ static void amdgpu_ras_do_recovery(struct work_struct *work) 
		amdgpu_device_gpu_recover(ras->adev, NULL, &reset_context);

	}

	atomic_set(&ras->in_recovery, 0);

	if (hive) {

		atomic_set(&hive->ras_recovery, 0);

		amdgpu_put_xgmi_hive(hive);

	}

}



/* alloc/realloc bps array */

drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h

+1 −0
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ struct amdgpu_hive_info { 


	struct amdgpu_reset_domain *reset_domain;

	uint32_t device_remove_count;

	atomic_t ras_recovery;

};



struct amdgpu_pcs_ras_field {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

+9 −1
Original line number Diff line number Diff line
@@ -2136,16 +2136,24 @@ static int smu_v13_0_6_get_thermal_temperature_range(struct smu_context *smu, 
static int smu_v13_0_6_mode1_reset(struct smu_context *smu)

{

	struct amdgpu_device *adev = smu->adev;

	struct amdgpu_hive_info *hive = NULL;

	u32 hive_ras_recovery = 0;

	struct amdgpu_ras *ras;

	u32 fatal_err, param;

	int ret = 0;



	hive = amdgpu_get_xgmi_hive(adev);

	ras = amdgpu_ras_get_context(adev);

	fatal_err = 0;

	param = SMU_RESET_MODE_1;



	if (hive) {

		hive_ras_recovery = atomic_read(&hive->ras_recovery);

		amdgpu_put_xgmi_hive(hive);

	}



	/* fatal error triggered by ras, PMFW supports the flag */

	if (ras && atomic_read(&ras->in_recovery))

	if (ras && (atomic_read(&ras->in_recovery) || hive_ras_recovery))

		fatal_err = 1;



	param |= (fatal_err << 16);