Commit 0c9ed604 authored by Chaitanya Dhere's avatar Chaitanya Dhere Committed by Alex Deucher
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drm/amd/display: FCLK P-state support updates 



[Why]
Previously we used to send FCLK P-state enable messages upon each call
to update_clocks based on dml output. This resulted in increased message
transactions between DC and PMFW.

[How]
Update the code to check safe_to_lower status and send the message based
on dml input only on boot. This reduces message transactions. Also
remove other unwanted code based on current code status.

Signed-off-by: default avatarChaitanya Dhere <chaitanya.dhere@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e127306d

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

+7 −4
Original line number Diff line number Diff line
@@ -284,7 +284,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, 
	bool dpp_clock_lowered = false;

	struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;

	bool force_reset = false;

	bool update_uclk = false;

	bool update_uclk = false, update_fclk = false;

	bool p_state_change_support;

	bool fclk_p_state_change_support;

	int total_plane_count;
@@ -371,14 +371,17 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, 
			update_uclk = true;

		}



		/* Always update saved value, even if new value not set due to P-State switching unsupported. Also check safe_to_lower for FCLK */

		if (safe_to_lower && (clk_mgr_base->clks.fclk_p_state_change_support != clk_mgr_base->clks.fclk_prev_p_state_change_support)) {

			update_fclk = true;

		}



		/* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */

		if (clk_mgr_base->clks.p_state_change_support &&

				(update_uclk || !clk_mgr_base->clks.prev_p_state_change_support))

			dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));



		if (clk_mgr_base->clks.fclk_p_state_change_support &&

				(update_uclk || !clk_mgr_base->clks.fclk_prev_p_state_change_support)) {



		if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && clk_mgr_base->clks.fclk_p_state_change_support && update_fclk) {

			/* Handle the code for sending a message to PMFW that FCLK P-state change is supported */

			dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_SUPPORTED);

		}

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h

+0 −1
Original line number Diff line number Diff line
@@ -33,7 +33,6 @@ 
#define FCLK_PSTATE_SUPPORTED          0x01



/* TODO Remove this MSG ID define after it becomes available in dalsmc */

#define DALSMC_MSG_SetFclkSwitchAllow	0x11

#define DALSMC_MSG_SetCabForUclkPstate	0x12

#define DALSMC_Result_OK				0x1