Commit 0c9dde0d authored by Jonathan Marek's avatar Jonathan Marek Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sm8150: Add secondary USB and PHY nodes 



Add dts nodes for the secondary USB controller and related PHY nodes.

Signed-off-by: default avatarJonathan Marek <jonathan@marek.ca>
Link: https://lore.kernel.org/r/20200609194030.17756-6-jonathan@marek.ca


Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent a89441fc

arch/arm64/boot/dts/qcom/sm8150.dtsi

+89 −0
Original line number Diff line number Diff line
@@ -845,6 +845,19 @@ 
			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;

		};



		usb_2_hsphy: phy@88e3000 {

			compatible = "qcom,sm8150-usb-hs-phy",

				     "qcom,usb-snps-hs-7nm-phy";

			reg = <0 0x088e3000 0 0x400>;

			status = "disabled";

			#phy-cells = <0>;



			clocks = <&rpmhcc RPMH_CXO_CLK>;

			clock-names = "ref";



			resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;

		};



		usb_1_qmpphy: phy@88e9000 {

			compatible = "qcom,sm8150-qmp-usb3-phy";

			reg = <0 0x088e9000 0 0x18c>,
@@ -894,6 +907,37 @@ 
			qcom,bcm-voters = <&apps_bcm_voter>;

		};



		usb_2_qmpphy: phy@88eb000 {

			compatible = "qcom,sm8150-qmp-usb3-uni-phy";

			reg = <0 0x088eb000 0 0x200>;

			status = "disabled";

			#clock-cells = <1>;

			#address-cells = <2>;

			#size-cells = <2>;

			ranges;



			clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,

				 <&rpmhcc RPMH_CXO_CLK>,

				 <&gcc GCC_USB3_SEC_CLKREF_CLK>,

				 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;

			clock-names = "aux", "ref_clk_src", "ref", "com_aux";



			resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,

				 <&gcc GCC_USB3_PHY_SEC_BCR>;

			reset-names = "phy", "common";



			usb_2_ssphy: lane@88eb200 {

				reg = <0 0x088eb200 0 0x200>,

				      <0 0x088eb400 0 0x200>,

				      <0 0x088eb800 0 0x800>,

				      <0 0x088eb600 0 0x200>;

				#phy-cells = <0>;

				clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;

				clock-names = "pipe0";

				clock-output-names = "usb3_uni_phy_pipe_clk_src";

			};

		};



		usb_1: usb@a6f8800 {

			compatible = "qcom,sm8150-dwc3", "qcom,dwc3";

			reg = <0 0x0a6f8800 0 0x400>;
@@ -946,6 +990,51 @@ 
			qcom,bcm-voters = <&apps_bcm_voter>;

		};



		usb_2: usb@a8f8800 {

			compatible = "qcom,sm8150-dwc3", "qcom,dwc3";

			reg = <0 0x0a8f8800 0 0x400>;

			status = "disabled";

			#address-cells = <2>;

			#size-cells = <2>;

			ranges;

			dma-ranges;



			clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,

				 <&gcc GCC_USB30_SEC_MASTER_CLK>,

				 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,

				 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,

				 <&gcc GCC_USB30_SEC_SLEEP_CLK>,

				 <&gcc GCC_USB3_SEC_CLKREF_CLK>;

			clock-names = "cfg_noc", "core", "iface", "mock_utmi",

				      "sleep", "xo";



			assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,

					  <&gcc GCC_USB30_SEC_MASTER_CLK>;

			assigned-clock-rates = <19200000>, <200000000>;



			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hs_phy_irq", "ss_phy_irq",

					  "dm_hs_phy_irq", "dp_hs_phy_irq";



			power-domains = <&gcc USB30_SEC_GDSC>;



			resets = <&gcc GCC_USB30_SEC_BCR>;



			usb_2_dwc3: dwc3@a800000 {

				compatible = "snps,dwc3";

				reg = <0 0x0a800000 0 0xcd00>;

				interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;

				iommus = <&apps_smmu 0x160 0>;

				snps,dis_u2_susphy_quirk;

				snps,dis_enblslpm_quirk;

				phys = <&usb_2_hsphy>, <&usb_2_ssphy>;

				phy-names = "usb2-phy", "usb3-phy";

			};

		};



		aoss_qmp: power-controller@c300000 {

			compatible = "qcom,sm8150-aoss-qmp";

			reg = <0x0 0x0c300000 0x0 0x100000>;