Loading drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c +20 −12 Original line number Diff line number Diff line Loading @@ -78,28 +78,33 @@ int mlx5_cmd_create_flow_table(struct mlx5_core_dev *dev, MLX5_CMD_OP_CREATE_FLOW_TABLE); MLX5_SET(create_flow_table_in, in, table_type, type); MLX5_SET(create_flow_table_in, in, level, level); MLX5_SET(create_flow_table_in, in, log_size, log_size); MLX5_SET(create_flow_table_in, in, flow_table_context.level, level); MLX5_SET(create_flow_table_in, in, flow_table_context.log_size, log_size); if (vport) { MLX5_SET(create_flow_table_in, in, vport_number, vport); MLX5_SET(create_flow_table_in, in, other_vport, 1); } MLX5_SET(create_flow_table_in, in, decap_en, en_encap_decap); MLX5_SET(create_flow_table_in, in, encap_en, en_encap_decap); MLX5_SET(create_flow_table_in, in, flow_table_context.decap_en, en_encap_decap); MLX5_SET(create_flow_table_in, in, flow_table_context.encap_en, en_encap_decap); switch (op_mod) { case FS_FT_OP_MOD_NORMAL: if (next_ft) { MLX5_SET(create_flow_table_in, in, table_miss_mode, 1); MLX5_SET(create_flow_table_in, in, table_miss_id, next_ft->id); MLX5_SET(create_flow_table_in, in, flow_table_context.table_miss_action, 1); MLX5_SET(create_flow_table_in, in, flow_table_context.table_miss_id, next_ft->id); } break; case FS_FT_OP_MOD_LAG_DEMUX: MLX5_SET(create_flow_table_in, in, op_mod, 0x1); if (next_ft) MLX5_SET(create_flow_table_in, in, lag_master_next_table_id, MLX5_SET(create_flow_table_in, in, flow_table_context.lag_master_next_table_id, next_ft->id); break; } Loading Loading @@ -146,10 +151,10 @@ int mlx5_cmd_modify_flow_table(struct mlx5_core_dev *dev, MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID); if (next_ft) { MLX5_SET(modify_flow_table_in, in, lag_master_next_table_id, next_ft->id); flow_table_context.lag_master_next_table_id, next_ft->id); } else { MLX5_SET(modify_flow_table_in, in, lag_master_next_table_id, 0); flow_table_context.lag_master_next_table_id, 0); } } else { if (ft->vport) { Loading @@ -160,11 +165,14 @@ int mlx5_cmd_modify_flow_table(struct mlx5_core_dev *dev, MLX5_SET(modify_flow_table_in, in, modify_field_select, MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID); if (next_ft) { MLX5_SET(modify_flow_table_in, in, table_miss_mode, 1); MLX5_SET(modify_flow_table_in, in, table_miss_id, MLX5_SET(modify_flow_table_in, in, flow_table_context.table_miss_action, 1); MLX5_SET(modify_flow_table_in, in, flow_table_context.table_miss_id, next_ft->id); } else { MLX5_SET(modify_flow_table_in, in, table_miss_mode, 0); MLX5_SET(modify_flow_table_in, in, flow_table_context.table_miss_action, 0); } } Loading include/linux/mlx5/mlx5_ifc.h +20 −26 Original line number Diff line number Diff line Loading @@ -6627,6 +6627,24 @@ struct mlx5_ifc_create_flow_table_out_bits { u8 reserved_at_60[0x20]; }; struct mlx5_ifc_flow_table_context_bits { u8 encap_en[0x1]; u8 decap_en[0x1]; u8 reserved_at_2[0x2]; u8 table_miss_action[0x4]; u8 level[0x8]; u8 reserved_at_10[0x8]; u8 log_size[0x8]; u8 reserved_at_20[0x8]; u8 table_miss_id[0x18]; u8 reserved_at_40[0x8]; u8 lag_master_next_table_id[0x18]; u8 reserved_at_60[0xe0]; }; struct mlx5_ifc_create_flow_table_in_bits { u8 opcode[0x10]; u8 reserved_at_10[0x10]; Loading @@ -6645,21 +6663,7 @@ struct mlx5_ifc_create_flow_table_in_bits { u8 reserved_at_a0[0x20]; u8 encap_en[0x1]; u8 decap_en[0x1]; u8 reserved_at_c2[0x2]; u8 table_miss_mode[0x4]; u8 level[0x8]; u8 reserved_at_d0[0x8]; u8 log_size[0x8]; u8 reserved_at_e0[0x8]; u8 table_miss_id[0x18]; u8 reserved_at_100[0x8]; u8 lag_master_next_table_id[0x18]; u8 reserved_at_120[0x80]; struct mlx5_ifc_flow_table_context_bits flow_table_context; }; struct mlx5_ifc_create_flow_group_out_bits { Loading Loading @@ -8277,17 +8281,7 @@ struct mlx5_ifc_modify_flow_table_in_bits { u8 reserved_at_a0[0x8]; u8 table_id[0x18]; u8 reserved_at_c0[0x4]; u8 table_miss_mode[0x4]; u8 reserved_at_c8[0x18]; u8 reserved_at_e0[0x8]; u8 table_miss_id[0x18]; u8 reserved_at_100[0x8]; u8 lag_master_next_table_id[0x18]; u8 reserved_at_120[0x80]; struct mlx5_ifc_flow_table_context_bits flow_table_context; }; struct mlx5_ifc_ets_tcn_config_reg_bits { Loading Loading
drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c +20 −12 Original line number Diff line number Diff line Loading @@ -78,28 +78,33 @@ int mlx5_cmd_create_flow_table(struct mlx5_core_dev *dev, MLX5_CMD_OP_CREATE_FLOW_TABLE); MLX5_SET(create_flow_table_in, in, table_type, type); MLX5_SET(create_flow_table_in, in, level, level); MLX5_SET(create_flow_table_in, in, log_size, log_size); MLX5_SET(create_flow_table_in, in, flow_table_context.level, level); MLX5_SET(create_flow_table_in, in, flow_table_context.log_size, log_size); if (vport) { MLX5_SET(create_flow_table_in, in, vport_number, vport); MLX5_SET(create_flow_table_in, in, other_vport, 1); } MLX5_SET(create_flow_table_in, in, decap_en, en_encap_decap); MLX5_SET(create_flow_table_in, in, encap_en, en_encap_decap); MLX5_SET(create_flow_table_in, in, flow_table_context.decap_en, en_encap_decap); MLX5_SET(create_flow_table_in, in, flow_table_context.encap_en, en_encap_decap); switch (op_mod) { case FS_FT_OP_MOD_NORMAL: if (next_ft) { MLX5_SET(create_flow_table_in, in, table_miss_mode, 1); MLX5_SET(create_flow_table_in, in, table_miss_id, next_ft->id); MLX5_SET(create_flow_table_in, in, flow_table_context.table_miss_action, 1); MLX5_SET(create_flow_table_in, in, flow_table_context.table_miss_id, next_ft->id); } break; case FS_FT_OP_MOD_LAG_DEMUX: MLX5_SET(create_flow_table_in, in, op_mod, 0x1); if (next_ft) MLX5_SET(create_flow_table_in, in, lag_master_next_table_id, MLX5_SET(create_flow_table_in, in, flow_table_context.lag_master_next_table_id, next_ft->id); break; } Loading Loading @@ -146,10 +151,10 @@ int mlx5_cmd_modify_flow_table(struct mlx5_core_dev *dev, MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID); if (next_ft) { MLX5_SET(modify_flow_table_in, in, lag_master_next_table_id, next_ft->id); flow_table_context.lag_master_next_table_id, next_ft->id); } else { MLX5_SET(modify_flow_table_in, in, lag_master_next_table_id, 0); flow_table_context.lag_master_next_table_id, 0); } } else { if (ft->vport) { Loading @@ -160,11 +165,14 @@ int mlx5_cmd_modify_flow_table(struct mlx5_core_dev *dev, MLX5_SET(modify_flow_table_in, in, modify_field_select, MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID); if (next_ft) { MLX5_SET(modify_flow_table_in, in, table_miss_mode, 1); MLX5_SET(modify_flow_table_in, in, table_miss_id, MLX5_SET(modify_flow_table_in, in, flow_table_context.table_miss_action, 1); MLX5_SET(modify_flow_table_in, in, flow_table_context.table_miss_id, next_ft->id); } else { MLX5_SET(modify_flow_table_in, in, table_miss_mode, 0); MLX5_SET(modify_flow_table_in, in, flow_table_context.table_miss_action, 0); } } Loading
include/linux/mlx5/mlx5_ifc.h +20 −26 Original line number Diff line number Diff line Loading @@ -6627,6 +6627,24 @@ struct mlx5_ifc_create_flow_table_out_bits { u8 reserved_at_60[0x20]; }; struct mlx5_ifc_flow_table_context_bits { u8 encap_en[0x1]; u8 decap_en[0x1]; u8 reserved_at_2[0x2]; u8 table_miss_action[0x4]; u8 level[0x8]; u8 reserved_at_10[0x8]; u8 log_size[0x8]; u8 reserved_at_20[0x8]; u8 table_miss_id[0x18]; u8 reserved_at_40[0x8]; u8 lag_master_next_table_id[0x18]; u8 reserved_at_60[0xe0]; }; struct mlx5_ifc_create_flow_table_in_bits { u8 opcode[0x10]; u8 reserved_at_10[0x10]; Loading @@ -6645,21 +6663,7 @@ struct mlx5_ifc_create_flow_table_in_bits { u8 reserved_at_a0[0x20]; u8 encap_en[0x1]; u8 decap_en[0x1]; u8 reserved_at_c2[0x2]; u8 table_miss_mode[0x4]; u8 level[0x8]; u8 reserved_at_d0[0x8]; u8 log_size[0x8]; u8 reserved_at_e0[0x8]; u8 table_miss_id[0x18]; u8 reserved_at_100[0x8]; u8 lag_master_next_table_id[0x18]; u8 reserved_at_120[0x80]; struct mlx5_ifc_flow_table_context_bits flow_table_context; }; struct mlx5_ifc_create_flow_group_out_bits { Loading Loading @@ -8277,17 +8281,7 @@ struct mlx5_ifc_modify_flow_table_in_bits { u8 reserved_at_a0[0x8]; u8 table_id[0x18]; u8 reserved_at_c0[0x4]; u8 table_miss_mode[0x4]; u8 reserved_at_c8[0x18]; u8 reserved_at_e0[0x8]; u8 table_miss_id[0x18]; u8 reserved_at_100[0x8]; u8 lag_master_next_table_id[0x18]; u8 reserved_at_120[0x80]; struct mlx5_ifc_flow_table_context_bits flow_table_context; }; struct mlx5_ifc_ets_tcn_config_reg_bits { Loading