Commit 0c8c2c9c authored by Christophe Leroy's avatar Christophe Leroy Committed by Michael Ellerman
Browse files

powerpc/8xx: Move DTLB perf handling closer. 



Now that space have been freed next to the DTLB miss handler,
it's associated DTLB perf handling can be brought back in
the same place.

Signed-off-by: default avatarChristophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/97f48cc1a2ea6b895bfac0752cbe59deaf2eecda.1589866984.git.christophe.leroy@csgroup.eu
parent 1251288e

arch/powerpc/kernel/head_8xx.S

+11 −12
Original line number Diff line number Diff line
@@ -344,6 +344,17 @@ DataStoreTLBMiss: 
	rfi

	patch_site	0b, patch__dtlbmiss_exit_1



#ifdef CONFIG_PERF_EVENTS

	patch_site	0f, patch__dtlbmiss_perf

0:	lwz	r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0)

	addi	r10, r10, 1

	stw	r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0)

	mfspr	r10, SPRN_DAR

	mtspr	SPRN_DAR, r11	/* Tag DAR */

	mfspr	r11, SPRN_M_TW

	rfi

#endif



/* This is an instruction TLB error on the MPC8xx.  This could be due

 * to many reasons, such as executing guarded memory or illegal instruction

 * addresses.  There is nothing to do but handle a big time error fault.
@@ -390,18 +401,6 @@ DARFixed:/* Return from dcbx instruction bug workaround */ 
	/* 0x300 is DataAccess exception, needed by bad_page_fault() */

	EXC_XFER_LITE(0x300, handle_page_fault)



/* Called from DataStoreTLBMiss when perf TLB misses events are activated */

#ifdef CONFIG_PERF_EVENTS

	patch_site	0f, patch__dtlbmiss_perf

0:	lwz	r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0)

	addi	r10, r10, 1

	stw	r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0)

	mfspr	r10, SPRN_DAR

	mtspr	SPRN_DAR, r11	/* Tag DAR */

	mfspr	r11, SPRN_M_TW

	rfi

#endif



stack_overflow:

	vmap_stack_overflow_exception