Commit 0c8a32ee authored by Guo Ren's avatar Guo Ren
Browse files

csky: Add memory layout 2.5G(user):1.5G(kernel) 



There are two ways for translating va to pa for csky:
 - Use TLB(Translate Lookup Buffer) and PTW (Page Table Walk)
 - Use SSEG0/1 (Simple Segment Mapping)

We use tlb mapping 0-2G and 3G-4G virtual address area and SSEG0/1
are for 2G-2.5G and 2.5G-3G translation. We could disable SSEG0
to use 2G-2.5G as TLB user mapping.

Signed-off-by: default avatarGuo Ren <guoren@linux.alibaba.com>
parent 7c53f6b6

arch/csky/Kconfig

+16 −0
Original line number Diff line number Diff line
@@ -192,6 +192,22 @@ config CPU_CK860 
endchoice



choice

	prompt "PAGE OFFSET"

	default PAGE_OFFSET_80000000



config PAGE_OFFSET_80000000

	bool "PAGE OFFSET 2G (user:kernel = 2:2)"



config PAGE_OFFSET_A0000000

	bool "PAGE OFFSET 2.5G (user:kernel = 2.5:1.5)"

endchoice



config PAGE_OFFSET

	hex

	default 0x80000000 if PAGE_OFFSET_80000000

	default 0xa0000000 if PAGE_OFFSET_A0000000

choice



	prompt "C-SKY PMU type"

	depends on PERF_EVENTS

	depends on CPU_CK807 || CPU_CK810 || CPU_CK860

arch/csky/abiv1/inc/abi/ckmmu.h

+4 −4
Original line number Diff line number Diff line
@@ -89,13 +89,13 @@ static inline void tlb_invalid_indexed(void) 
	cpwcr("cpcr8", 0x02000000);

}



static inline void setup_pgd(unsigned long pgd, bool kernel)

static inline void setup_pgd(pgd_t *pgd)

{

	cpwcr("cpcr29", pgd | BIT(0));

	cpwcr("cpcr29", __pa(pgd) | BIT(0));

}



static inline unsigned long get_pgd(void)

static inline pgd_t *get_pgd(void)

{

	return cprcr("cpcr29") & ~BIT(0);

	return __va(cprcr("cpcr29") & ~BIT(0));

}

#endif /* __ASM_CSKY_CKMMUV1_H */

arch/csky/abiv2/inc/abi/ckmmu.h

+7 −7
Original line number Diff line number Diff line
@@ -100,16 +100,16 @@ static inline void tlb_invalid_indexed(void) 
	mtcr("cr<8, 15>", 0x02000000);

}



static inline void setup_pgd(unsigned long pgd, bool kernel)

static inline void setup_pgd(pgd_t *pgd)

{

	if (kernel)

		mtcr("cr<28, 15>", pgd | BIT(0));

	else

		mtcr("cr<29, 15>", pgd | BIT(0));

#ifdef CONFIG_CPU_HAS_TLBI

	mtcr("cr<28, 15>", __pa(pgd) | BIT(0));

#endif

	mtcr("cr<29, 15>", __pa(pgd) | BIT(0));

}



static inline unsigned long get_pgd(void)

static inline pgd_t *get_pgd(void)

{

	return mfcr("cr<29, 15>") & ~BIT(0);

	return __va(mfcr("cr<29, 15>") & ~BIT(0));

}

#endif /* __ASM_CSKY_CKMMUV2_H */

arch/csky/abiv2/inc/abi/entry.h

+16 −3
Original line number Diff line number Diff line
@@ -26,6 +26,9 @@ 
	stw	tls, (sp, 0)

	stw	lr, (sp, 4)



	RD_MEH	lr

	WR_MEH	lr



	mfcr	lr, epc

	movi	tls, \epc_inc

	add	lr, tls
@@ -231,6 +234,16 @@ 
	mtcr	\rx, cr<8, 15>

.endm



#ifdef CONFIG_PAGE_OFFSET_80000000

#define MSA_SET cr<30, 15>

#define MSA_CLR cr<31, 15>

#endif



#ifdef CONFIG_PAGE_OFFSET_A0000000

#define MSA_SET cr<31, 15>

#define MSA_CLR cr<30, 15>

#endif



.macro SETUP_MMU

	/* Init psr and enable ee */

	lrw	r6, DEFAULT_PSR_VALUE
@@ -281,15 +294,15 @@ 
	 * 31 - 29 | 28 - 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

	 *   BA     Reserved  SH  WA  B   SO SEC  C   D   V

	 */

	mfcr	r6, cr<30, 15> /* Get MSA0 */

	mfcr	r6, MSA_SET /* Get MSA */

2:

	lsri	r6, 29

	lsli	r6, 29

	addi	r6, 0x1ce

	mtcr	r6, cr<30, 15> /* Set MSA0 */

	mtcr	r6, MSA_SET /* Set MSA */



	movi    r6, 0

	mtcr	r6, cr<31, 15> /* Clr MSA1 */

	mtcr	r6, MSA_CLR /* Clr MSA */



	/* enable MMU */

	mfcr    r6, cr18

arch/csky/include/asm/memory.h

+1 −1
Original line number Diff line number Diff line
@@ -10,7 +10,7 @@ 


#define FIXADDR_TOP	_AC(0xffffc000, UL)

#define PKMAP_BASE	_AC(0xff800000, UL)

#define VMALLOC_START	_AC(0xc0008000, UL)

#define VMALLOC_START	(PAGE_OFFSET + LOWMEM_LIMIT + (PAGE_SIZE * 8))

#define VMALLOC_END	(PKMAP_BASE - (PAGE_SIZE * 2))



#ifdef CONFIG_HAVE_TCM