Commit 0c7ea2b1 authored by JC Kuo's avatar JC Kuo Committed by Thierry Reding
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clk: tegra: Don't enable PLLE HW sequencer at init 



PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware
power sequencers' output to enable/disable PLLE. PLLE hardware power
sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers
are enabled.

Signed-off-by: default avatarJC Kuo <jckuo@nvidia.com>
Acked-by: default avatarThierry Reding <treding@nvidia.com>
Acked-by: default avatarStephen Boyd <sboyd@kernel.org>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 54443ef6

drivers/clk/tegra/clk-pll.c

+0 −12
Original line number Diff line number Diff line
@@ -2515,18 +2515,6 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw) 
	pll_writel(val, PLLE_SS_CTRL, pll);

	udelay(1);



	val = pll_readl_misc(pll);

	val &= ~PLLE_MISC_IDDQ_SW_CTRL;

	pll_writel_misc(val, pll);



	val = pll_readl(pll->params->aux_reg, pll);

	val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE);

	val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);

	pll_writel(val, pll->params->aux_reg, pll);

	udelay(1);

	val |= PLLE_AUX_SEQ_ENABLE;

	pll_writel(val, pll->params->aux_reg, pll);



out:

	if (pll->lock)

		spin_unlock_irqrestore(pll->lock, flags);