Commit 0c65dc06 authored by Dnyaneshwar Bhadane's avatar Dnyaneshwar Bhadane Committed by Radhakrishna Sripada
Browse files

drm/i915/jsl: s/JSL/JASPERLAKE for platform/subplatform defines 



Follow consistent naming convention. Replace JSL with
JASPERLAKE. Unroll IS_JSL_EHL() define  with IS_JASPERLAKE() ||
IS_ELKHARTLAKE() condition. Change in the display step define for
Jasperlake.

v2:
- Change subject prefix skl instead of SKL(Anusha)

v3:
- Remove the use of define IS_JSL_EHL.
- Replace with IS_JASPERLAKE() || IS_ELKHARTLAKE()
- Unrolled wrapper IS_JSL_ELK_DISPLAY_STEP (Jani/Tvrtko)

v4:
- Removed unused macro

v5:
- Resolved valid checkpatch warning(Jani)

Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: default avatarDnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Acked-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230801135344.3797924-9-dnyaneshwar.bhadane@intel.com
parent e5490979

drivers/gpu/drm/i915/display/icl_dsi.c

+3 −2
Original line number Diff line number Diff line
@@ -444,7 +444,8 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) 
		intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);



		/* For EHL, TGL, set latency optimization for PCS_DW1 lanes */

		if (IS_JSL_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 12)) {

		if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv) ||

		    (DISPLAY_VER(dev_priv) >= 12)) {

			intel_de_rmw(dev_priv, ICL_PORT_PCS_DW1_AUX(phy),

				     LATENCY_OPTIM_MASK, LATENCY_OPTIM_VAL(0));
@@ -553,7 +554,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder, 
		}

	}



	if (IS_JSL_EHL(dev_priv)) {

	if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {

		for_each_dsi_phy(phy, intel_dsi->phys)

			intel_de_rmw(dev_priv, ICL_DPHY_CHKN(phy),

				     0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP);

drivers/gpu/drm/i915/display/intel_cdclk.c

+2 −2
Original line number Diff line number Diff line
@@ -3155,7 +3155,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) 
 */

void intel_update_max_cdclk(struct drm_i915_private *dev_priv)

{

	if (IS_JSL_EHL(dev_priv)) {

	if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {

		if (dev_priv->display.cdclk.hw.ref == 24000)

			dev_priv->display.cdclk.max_cdclk_freq = 552000;

		else
@@ -3583,7 +3583,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) 
	} else if (DISPLAY_VER(dev_priv) >= 12) {

		dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;

		dev_priv->display.cdclk.table = icl_cdclk_table;

	} else if (IS_JSL_EHL(dev_priv)) {

	} else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {

		dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs;

		dev_priv->display.cdclk.table = icl_cdclk_table;

	} else if (DISPLAY_VER(dev_priv) >= 11) {

drivers/gpu/drm/i915/display/intel_combo_phy.c

+4 −3
Original line number Diff line number Diff line
@@ -141,7 +141,7 @@ static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy) 


	if (IS_ALDERLAKE_S(i915))

		return phy == PHY_A;

	else if (IS_JSL_EHL(i915) ||

	else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) ||

		 IS_ROCKETLAKE(i915) ||

		 IS_DG1(i915))

		return phy < PHY_C;
@@ -242,7 +242,7 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv, 
		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),

				     IREFGEN, IREFGEN);



		if (IS_JSL_EHL(dev_priv)) {

		if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {

			if (ehl_vbt_ddi_d_present(dev_priv))

				expected_val = ICL_PHY_MISC_MUX_DDID;
@@ -333,7 +333,8 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv) 
		 * "internal" child devices.

		 */

		val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));

		if (IS_JSL_EHL(dev_priv) && phy == PHY_A) {

		if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) &&

		    phy == PHY_A) {

			val &= ~ICL_PHY_MISC_MUX_DDID;



			if (ehl_vbt_ddi_d_present(dev_priv))

drivers/gpu/drm/i915/display/intel_ddi.c

+4 −3
Original line number Diff line number Diff line
@@ -3583,7 +3583,8 @@ void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, 
{

	if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000)

		crtc_state->min_voltage_level = 2;

	else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000)

	else if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) &&

		 crtc_state->port_clock > 594000)

		crtc_state->min_voltage_level = 3;

	else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000)

		crtc_state->min_voltage_level = 1;
@@ -4878,7 +4879,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, 
		encoder->disable_clock = dg1_ddi_disable_clock;

		encoder->is_clock_enabled = dg1_ddi_is_clock_enabled;

		encoder->get_config = dg1_ddi_get_config;

	} else if (IS_JSL_EHL(dev_priv)) {

	} else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {

		if (intel_ddi_is_tc(dev_priv, port)) {

			encoder->enable_clock = jsl_ddi_tc_enable_clock;

			encoder->disable_clock = jsl_ddi_tc_disable_clock;
@@ -4949,7 +4950,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, 
		encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);

	else if (DISPLAY_VER(dev_priv) >= 12)

		encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);

	else if (IS_JSL_EHL(dev_priv))

	else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))

		encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);

	else if (DISPLAY_VER(dev_priv) == 11)

		encoder->hpd_pin = icl_hpd_pin(dev_priv, port);

drivers/gpu/drm/i915/display/intel_display.c

+3 −2
Original line number Diff line number Diff line
@@ -1749,7 +1749,7 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) 
		return phy <= PHY_E;

	else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))

		return phy <= PHY_D;

	else if (IS_JSL_EHL(dev_priv))

	else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))

		return phy <= PHY_C;

	else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12))

		return phy <= PHY_B;
@@ -1801,7 +1801,8 @@ enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) 
		return PHY_B + port - PORT_TC1;

	else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)

		return PHY_C + port - PORT_TC1;

	else if (IS_JSL_EHL(i915) && port == PORT_D)

	else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&

		 port == PORT_D)

		return PHY_A;



	return PHY_A + port - PORT_A;