Commit 0c3e94c2 authored by Bruce Allan's avatar Bruce Allan Committed by Tony Nguyen
Browse files

ice: cleanup style issues 



A few style issues reported by checkpatch have snuck into the code; resolve
the style issues.

COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses

Signed-off-by: default avatarBruce Allan <bruce.w.allan@intel.com>
Tested-by: default avatarTony Brelinski <tonyx.brelinski@intel.com>
Signed-off-by: default avatarTony Nguyen <anthony.l.nguyen@intel.com>
parent e97fb1ae

drivers/net/ethernet/intel/ice/ice_controlq.h

+2 −2
Original line number Diff line number Diff line
@@ -14,8 +14,8 @@ 
	(&(((struct ice_aq_desc *)((R).desc_buf.va))[i]))



#define ICE_CTL_Q_DESC_UNUSED(R) \

	(u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \

	      (R)->next_to_clean - (R)->next_to_use - 1)

	((u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \

	       (R)->next_to_clean - (R)->next_to_use - 1))



/* Defines that help manage the driver vs FW API checks.

 * Take a look at ice_aq_ver_check in ice_controlq.c for actual usage.

drivers/net/ethernet/intel/ice/ice_flex_type.h

+2 −2
Original line number Diff line number Diff line
@@ -497,8 +497,8 @@ struct ice_xlt1 { 
#define ICE_PF_NUM_S	13

#define ICE_PF_NUM_M	(0x07 << ICE_PF_NUM_S)

#define ICE_VSIG_VALUE(vsig, pf_id) \

	(u16)((((u16)(vsig)) & ICE_VSIG_IDX_M) | \

	      (((u16)(pf_id) << ICE_PF_NUM_S) & ICE_PF_NUM_M))

	((u16)((((u16)(vsig)) & ICE_VSIG_IDX_M) | \

	       (((u16)(pf_id) << ICE_PF_NUM_S) & ICE_PF_NUM_M)))

#define ICE_DEFAULT_VSIG	0



/* XLT2 Table */

drivers/net/ethernet/intel/ice/ice_flow.c

+3 −3
Original line number Diff line number Diff line
@@ -2008,9 +2008,9 @@ ice_add_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof) 
 * [63] - Encapsulation flag, 0 if non-tunneled, 1 if tunneled

 */

#define ICE_FLOW_GEN_PROFID(hash, hdr, segs_cnt) \

	(u64)(((u64)(hash) & ICE_FLOW_PROF_HASH_M) | \

	((u64)(((u64)(hash) & ICE_FLOW_PROF_HASH_M) | \

	       (((u64)(hdr) << ICE_FLOW_PROF_HDR_S) & ICE_FLOW_PROF_HDR_M) | \

	      ((u8)((segs_cnt) - 1) ? ICE_FLOW_PROF_ENCAP_M : 0))

	       ((u8)((segs_cnt) - 1) ? ICE_FLOW_PROF_ENCAP_M : 0)))



/**

 * ice_add_rss_cfg_sync - add an RSS configuration