Commit 0c29397a authored by Sean Christopherson's avatar Sean Christopherson Committed by Paolo Bonzini
Browse files

KVM: SVM: Disable SEV-ES support if MMIO caching is disable 



Disable SEV-ES if MMIO caching is disabled as SEV-ES relies on MMIO SPTEs
generating #NPF(RSVD), which are reflected by the CPU into the guest as
a #VC.  With SEV-ES, the untrusted host, a.k.a. KVM, doesn't have access
to the guest instruction stream or register state and so can't directly
emulate in response to a #NPF on an emulated MMIO GPA.  Disabling MMIO
caching means guest accesses to emulated MMIO ranges cause #NPF(!PRESENT),
and those flavors of #NPF cause automatic VM-Exits, not #VC.

Adjust KVM's MMIO masks to account for the C-bit location prior to doing
SEV(-ES) setup, and document that dependency between adjusting the MMIO
SPTE mask and SEV(-ES) setup.

Fixes: b09763da ("KVM: x86/mmu: Add module param to disable MMIO caching (for testing)")
Reported-by: default avatarMichael Roth <michael.roth@amd.com>
Tested-by: default avatarMichael Roth <michael.roth@amd.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: default avatarSean Christopherson <seanjc@google.com>
Message-Id: <20220803224957.1285926-4-seanjc@google.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent c3e0c8c2

arch/x86/kvm/mmu.h

+2 −0
Original line number Diff line number Diff line
@@ -6,6 +6,8 @@ 
#include "kvm_cache_regs.h"

#include "cpuid.h"



extern bool __read_mostly enable_mmio_caching;



#define PT_WRITABLE_SHIFT 1

#define PT_USER_SHIFT 2

arch/x86/kvm/mmu/spte.c

+1 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ 
bool __read_mostly enable_mmio_caching = true;

static bool __ro_after_init allow_mmio_caching;

module_param_named(mmio_caching, enable_mmio_caching, bool, 0444);

EXPORT_SYMBOL_GPL(enable_mmio_caching);



u64 __read_mostly shadow_host_writable_mask;

u64 __read_mostly shadow_mmu_writable_mask;

arch/x86/kvm/mmu/spte.h

+0 −2
Original line number Diff line number Diff line
@@ -5,8 +5,6 @@ 


#include "mmu_internal.h"



extern bool __read_mostly enable_mmio_caching;



/*

 * A MMU present SPTE is backed by actual memory and may or may not be present

 * in hardware.  E.g. MMIO SPTEs are not considered present.  Use bit 11, as it

arch/x86/kvm/svm/sev.c

+10 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ 
#include <asm/trapnr.h>

#include <asm/fpu/xcr.h>



#include "mmu.h"

#include "x86.h"

#include "svm.h"

#include "svm_ops.h"
@@ -2221,6 +2222,15 @@ void __init sev_hardware_setup(void) 
	if (!sev_es_enabled)

		goto out;



	/*

	 * SEV-ES requires MMIO caching as KVM doesn't have access to the guest

	 * instruction stream, i.e. can't emulate in response to a #NPF and

	 * instead relies on #NPF(RSVD) being reflected into the guest as #VC

	 * (the guest can then do a #VMGEXIT to request MMIO emulation).

	 */

	if (!enable_mmio_caching)

		goto out;



	/* Does the CPU support SEV-ES? */

	if (!boot_cpu_has(X86_FEATURE_SEV_ES))

		goto out;

arch/x86/kvm/svm/svm.c

+6 −3
Original line number Diff line number Diff line
@@ -5034,13 +5034,16 @@ static __init int svm_hardware_setup(void) 
	/* Setup shadow_me_value and shadow_me_mask */

	kvm_mmu_set_me_spte_mask(sme_me_mask, sme_me_mask);



	/* Note, SEV setup consumes npt_enabled. */

	svm_adjust_mmio_mask();



	/*

	 * Note, SEV setup consumes npt_enabled and enable_mmio_caching (which

	 * may be modified by svm_adjust_mmio_mask()).

	 */

	sev_hardware_setup();



	svm_hv_hardware_setup();



	svm_adjust_mmio_mask();



	for_each_possible_cpu(cpu) {

		r = svm_cpu_init(cpu);

		if (r)