Commit 0c1bc63a authored by Paul Greenwalt's avatar Paul Greenwalt Committed by Ye Bin
Browse files

ice: Add E830 device IDs, MAC type and registers 

stable inclusion
from stable-v6.6.81
commit 88f7ac6c4fceb40e667ece422bb256fb08953d29
category: bugfix
bugzilla: https://gitee.com/src-openeuler/kernel/issues/IBWVSV
CVE: CVE-2025-21883

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=88f7ac6c4fceb40e667ece422bb256fb08953d29



--------------------------------

[ Upstream commit ba1124f58afd37d9ff155d4ab7c9f209346aaed9 ]

E830 is the 200G NIC family which uses the ice driver.

Add specific E830 registers. Embed macros to use proper register based on
(hw)->mac_type & name those macros to [ORIGINAL]_BY_MAC(hw). Registers
only available on one of the macs will need to be explicitly referred to
as E800_NAME instead of just NAME. PTP is not yet supported.

Co-developed-by: default avatarMilena Olech <milena.olech@intel.com>
Signed-off-by: default avatarMilena Olech <milena.olech@intel.com>
Co-developed-by: default avatarDan Nowlin <dan.nowlin@intel.com>
Signed-off-by: default avatarDan Nowlin <dan.nowlin@intel.com>
Co-developed-by: default avatarScott Taylor <scott.w.taylor@intel.com>
Signed-off-by: default avatarScott Taylor <scott.w.taylor@intel.com>
Co-developed-by: default avatarPawel Chmielewski <pawel.chmielewski@intel.com>
Signed-off-by: default avatarPawel Chmielewski <pawel.chmielewski@intel.com>
Reviewed-by: default avatarSimon Horman <horms@kernel.org>
Signed-off-by: default avatarPaul Greenwalt <paul.greenwalt@intel.com>
Tested-by: default avatarTony Brelinski <tony.brelinski@intel.com>
Signed-off-by: default avatarJacob Keller <jacob.e.keller@intel.com>
Link: https://lore.kernel.org/r/20231025214157.1222758-2-jacob.e.keller@intel.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
Stable-dep-of: 79990cf5e7ad ("ice: Fix deinitializing VF in error path")
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
Signed-off-by: default avatarYe Bin <yebin10@huawei.com>
parent f070c1ba

drivers/net/ethernet/intel/ice/ice_common.c

+47 −24
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/* Copyright (c) 2018, Intel Corporation. */

/* Copyright (c) 2018-2023, Intel Corporation. */



#include "ice_common.h"

#include "ice_sched.h"
@@ -153,6 +153,12 @@ static int ice_set_mac_type(struct ice_hw *hw) 
	case ICE_DEV_ID_E823L_SFP:

		hw->mac_type = ICE_MAC_GENERIC;

		break;

	case ICE_DEV_ID_E830_BACKPLANE:

	case ICE_DEV_ID_E830_QSFP56:

	case ICE_DEV_ID_E830_SFP:

	case ICE_DEV_ID_E830_SFP_DD:

		hw->mac_type = ICE_MAC_E830;

		break;

	default:

		hw->mac_type = ICE_MAC_UNKNOWN;

		break;
@@ -684,8 +690,7 @@ static void 
ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw,

				struct ice_aqc_set_mac_cfg *cmd)

{

	u16 fc_thres_val, tx_timer_val;

	u32 val;

	u32 val, fc_thres_m;



	/* We read back the transmit timer and FC threshold value of

	 * LFC. Thus, we will use index =
@@ -694,19 +699,32 @@ ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 
	 * Also, because we are operating on transmit timer and FC

	 * threshold of LFC, we don't turn on any bit in tx_tmr_priority

	 */

#define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX

#define E800_IDX_OF_LFC E800_PRTMAC_HSEC_CTL_TX_PS_QNT_MAX

#define E800_REFRESH_TMR E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR



	if (hw->mac_type == ICE_MAC_E830) {

		/* Retrieve the transmit timer */

	val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));

	tx_timer_val = val &

		PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;

	cmd->tx_tmr_value = cpu_to_le16(tx_timer_val);

		val = rd32(hw, E830_PRTMAC_CL01_PS_QNT);

		cmd->tx_tmr_value =

			le16_encode_bits(val, E830_PRTMAC_CL01_PS_QNT_CL0_M);



	/* Retrieve the FC threshold */

	val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));

	fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M;

		/* Retrieve the fc threshold */

		val = rd32(hw, E830_PRTMAC_CL01_QNT_THR);

		fc_thres_m = E830_PRTMAC_CL01_QNT_THR_CL0_M;

	} else {

		/* Retrieve the transmit timer */

		val = rd32(hw,

			   E800_PRTMAC_HSEC_CTL_TX_PS_QNT(E800_IDX_OF_LFC));

		cmd->tx_tmr_value =

			le16_encode_bits(val,

					 E800_PRTMAC_HSEC_CTL_TX_PS_QNT_M);



	cmd->fc_refresh_threshold = cpu_to_le16(fc_thres_val);

		/* Retrieve the fc threshold */

		val = rd32(hw,

			   E800_REFRESH_TMR(E800_IDX_OF_LFC));

		fc_thres_m = E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR_M;

	}

	cmd->fc_refresh_threshold = le16_encode_bits(val, fc_thres_m);

}



/**
@@ -2389,16 +2407,21 @@ ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 
static void

ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p)

{

	u32 reg_val, val;

	u32 reg_val, gsize, bsize;



	reg_val = rd32(hw, GLQF_FD_SIZE);

	val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>

		GLQF_FD_SIZE_FD_GSIZE_S;

	func_p->fd_fltr_guar =

		ice_get_num_per_func(hw, val);

	val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>

		GLQF_FD_SIZE_FD_BSIZE_S;

	func_p->fd_fltr_best_effort = val;

	switch (hw->mac_type) {

	case ICE_MAC_E830:

		gsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_GSIZE_M, reg_val);

		bsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_BSIZE_M, reg_val);

		break;

	case ICE_MAC_E810:

	default:

		gsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_GSIZE_M, reg_val);

		bsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_BSIZE_M, reg_val);

	}

	func_p->fd_fltr_guar = ice_get_num_per_func(hw, gsize);

	func_p->fd_fltr_best_effort = bsize;



	ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n",

		  func_p->fd_fltr_guar);

drivers/net/ethernet/intel/ice/ice_devids.h

+9 −1
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/* Copyright (c) 2018, Intel Corporation. */

/* Copyright (c) 2018-2023, Intel Corporation. */



#ifndef _ICE_DEVIDS_H_

#define _ICE_DEVIDS_H_
@@ -16,6 +16,14 @@ 
#define ICE_DEV_ID_E823L_1GBE		0x124F

/* Intel(R) Ethernet Connection E823-L for QSFP */

#define ICE_DEV_ID_E823L_QSFP		0x151D

/* Intel(R) Ethernet Controller E830-C for backplane */

#define ICE_DEV_ID_E830_BACKPLANE	0x12D1

/* Intel(R) Ethernet Controller E830-C for QSFP */

#define ICE_DEV_ID_E830_QSFP56		0x12D2

/* Intel(R) Ethernet Controller E830-C for SFP */

#define ICE_DEV_ID_E830_SFP		0x12D3

/* Intel(R) Ethernet Controller E830-C for SFP-DD */

#define ICE_DEV_ID_E830_SFP_DD		0x12D4

/* Intel(R) Ethernet Controller E810-C for backplane */

#define ICE_DEV_ID_E810C_BACKPLANE	0x1591

/* Intel(R) Ethernet Controller E810-C for QSFP */

drivers/net/ethernet/intel/ice/ice_ethtool_fdir.c

+16 −8
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/* Copyright (C) 2018-2020, Intel Corporation. */

/* Copyright (C) 2018-2023, Intel Corporation. */



/* flow director ethtool support for ice */
@@ -540,16 +540,24 @@ int ice_fdir_num_avail_fltr(struct ice_hw *hw, struct ice_vsi *vsi) 
	/* total guaranteed filters assigned to this VSI */

	num_guar = vsi->num_gfltr;



	/* minus the guaranteed filters programed by this VSI */

	num_guar -= (rd32(hw, VSIQF_FD_CNT(vsi_num)) &

		     VSIQF_FD_CNT_FD_GCNT_M) >> VSIQF_FD_CNT_FD_GCNT_S;



	/* total global best effort filters */

	num_be = hw->func_caps.fd_fltr_best_effort;



	/* minus the global best effort filters programmed */

	num_be -= (rd32(hw, GLQF_FD_CNT) & GLQF_FD_CNT_FD_BCNT_M) >>

		   GLQF_FD_CNT_FD_BCNT_S;

	/* Subtract the number of programmed filters from the global values */

	switch (hw->mac_type) {

	case ICE_MAC_E830:

		num_guar -= FIELD_GET(E830_VSIQF_FD_CNT_FD_GCNT_M,

				      rd32(hw, VSIQF_FD_CNT(vsi_num)));

		num_be -= FIELD_GET(E830_GLQF_FD_CNT_FD_BCNT_M,

				    rd32(hw, GLQF_FD_CNT));

		break;

	case ICE_MAC_E810:

	default:

		num_guar -= FIELD_GET(E800_VSIQF_FD_CNT_FD_GCNT_M,

				      rd32(hw, VSIQF_FD_CNT(vsi_num)));

		num_be -= FIELD_GET(E800_GLQF_FD_CNT_FD_BCNT_M,

				    rd32(hw, GLQF_FD_CNT));

	}



	return num_guar + num_be;

}

drivers/net/ethernet/intel/ice/ice_hw_autogen.h

+39 −13
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/* Copyright (c) 2018, Intel Corporation. */

/* Copyright (c) 2018-2023, Intel Corporation. */



/* Machine-generated file */
@@ -284,11 +284,11 @@ 
#define VPLAN_TX_QBASE_VFNUMQ_M			ICE_M(0xFF, 16)

#define VPLAN_TXQ_MAPENA(_VF)			(0x00073800 + ((_VF) * 4))

#define VPLAN_TXQ_MAPENA_TX_ENA_M		BIT(0)

#define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(_i)	(0x001E36E0 + ((_i) * 32))

#define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 8

#define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M ICE_M(0xFFFF, 0)

#define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i) (0x001E3800 + ((_i) * 32))

#define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M ICE_M(0xFFFF, 0)

#define E800_PRTMAC_HSEC_CTL_TX_PS_QNT(_i)	(0x001E36E0 + ((_i) * 32))

#define E800_PRTMAC_HSEC_CTL_TX_PS_QNT_MAX	8

#define E800_PRTMAC_HSEC_CTL_TX_PS_QNT_M	GENMASK(15, 0)

#define E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR(_i)	(0x001E3800 + ((_i) * 32))

#define E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR_M	GENMASK(15, 0)

#define GL_MDCK_TX_TDPU				0x00049348

#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_M BIT(1)

#define GL_MDET_RX				0x00294C00
@@ -311,7 +311,11 @@ 
#define GL_MDET_TX_PQM_MAL_TYPE_S		26

#define GL_MDET_TX_PQM_MAL_TYPE_M		ICE_M(0x1F, 26)

#define GL_MDET_TX_PQM_VALID_M			BIT(31)

#define GL_MDET_TX_TCLAN			0x000FC068

#define GL_MDET_TX_TCLAN_BY_MAC(hw)				  \

	((hw)->mac_type == ICE_MAC_E830 ? E830_GL_MDET_TX_TCLAN : \

	 E800_GL_MDET_TX_TCLAN)

#define E800_GL_MDET_TX_TCLAN			0x000FC068

#define E830_GL_MDET_TX_TCLAN			0x000FCCC0

#define GL_MDET_TX_TCLAN_QNUM_S			0

#define GL_MDET_TX_TCLAN_QNUM_M			ICE_M(0x7FFF, 0)

#define GL_MDET_TX_TCLAN_VF_NUM_S		15
@@ -325,7 +329,11 @@ 
#define PF_MDET_RX_VALID_M			BIT(0)

#define PF_MDET_TX_PQM				0x002D2C80

#define PF_MDET_TX_PQM_VALID_M			BIT(0)

#define PF_MDET_TX_TCLAN			0x000FC000

#define PF_MDET_TX_TCLAN_BY_MAC(hw)				  \

	((hw)->mac_type == ICE_MAC_E830 ? E830_PF_MDET_TX_TCLAN : \

	 E800_PF_MDET_TX_TCLAN)

#define E800_PF_MDET_TX_TCLAN			0x000FC000

#define E830_PF_MDET_TX_TCLAN			0x000FCC00

#define PF_MDET_TX_TCLAN_VALID_M		BIT(0)

#define VP_MDET_RX(_VF)				(0x00294400 + ((_VF) * 4))

#define VP_MDET_RX_VALID_M			BIT(0)
@@ -335,6 +343,8 @@ 
#define VP_MDET_TX_TCLAN_VALID_M		BIT(0)

#define VP_MDET_TX_TDPU(_VF)			(0x00040000 + ((_VF) * 4))

#define VP_MDET_TX_TDPU_VALID_M			BIT(0)

#define E800_GL_MNG_FWSM_FW_MODES_M		GENMASK(2, 0)

#define E830_GL_MNG_FWSM_FW_MODES_M		GENMASK(1, 0)

#define GL_MNG_FWSM				0x000B6134

#define GL_MNG_FWSM_FW_LOADING_M		BIT(30)

#define GLNVM_FLA				0x000B6108
@@ -363,13 +373,18 @@ 
#define GL_PWR_MODE_CTL_CAR_MAX_BW_S		30

#define GL_PWR_MODE_CTL_CAR_MAX_BW_M		ICE_M(0x3, 30)

#define GLQF_FD_CNT				0x00460018

#define E800_GLQF_FD_CNT_FD_GCNT_M		GENMASK(14, 0)

#define E830_GLQF_FD_CNT_FD_GCNT_M		GENMASK(15, 0)

#define GLQF_FD_CNT_FD_BCNT_S			16

#define GLQF_FD_CNT_FD_BCNT_M			ICE_M(0x7FFF, 16)

#define E800_GLQF_FD_CNT_FD_BCNT_M		GENMASK(30, 16)

#define E830_GLQF_FD_CNT_FD_BCNT_M		GENMASK(31, 16)

#define GLQF_FD_SIZE				0x00460010

#define GLQF_FD_SIZE_FD_GSIZE_S			0

#define GLQF_FD_SIZE_FD_GSIZE_M			ICE_M(0x7FFF, 0)

#define E800_GLQF_FD_SIZE_FD_GSIZE_M		GENMASK(14, 0)

#define E830_GLQF_FD_SIZE_FD_GSIZE_M		GENMASK(15, 0)

#define GLQF_FD_SIZE_FD_BSIZE_S			16

#define GLQF_FD_SIZE_FD_BSIZE_M			ICE_M(0x7FFF, 16)

#define E800_GLQF_FD_SIZE_FD_BSIZE_M		GENMASK(30, 16)

#define E830_GLQF_FD_SIZE_FD_BSIZE_M		GENMASK(31, 16)

#define GLQF_FDINSET(_i, _j)			(0x00412000 + ((_i) * 4 + (_j) * 512))

#define GLQF_FDMASK(_i)				(0x00410800 + ((_i) * 4))

#define GLQF_FDMASK_MAX_INDEX			31
@@ -388,6 +403,10 @@ 
#define GLQF_HMASK_SEL(_i)			(0x00410000 + ((_i) * 4))

#define GLQF_HMASK_SEL_MAX_INDEX		127

#define GLQF_HMASK_SEL_MASK_SEL_S		0

#define E800_PFQF_FD_CNT_FD_GCNT_M		GENMASK(14, 0)

#define E830_PFQF_FD_CNT_FD_GCNT_M		GENMASK(15, 0)

#define E800_PFQF_FD_CNT_FD_BCNT_M		GENMASK(30, 16)

#define E830_PFQF_FD_CNT_FD_BCNT_M		GENMASK(31, 16)

#define PFQF_FD_ENA				0x0043A000

#define PFQF_FD_ENA_FD_ENA_M			BIT(0)

#define PFQF_FD_SIZE				0x00460100
@@ -478,6 +497,7 @@ 
#define GLTSYN_SYNC_DLAY			0x00088818

#define GLTSYN_TGT_H_0(_i)			(0x00088930 + ((_i) * 4))

#define GLTSYN_TGT_L_0(_i)			(0x00088928 + ((_i) * 4))

#define GLTSYN_TIME_0(_i)			(0x000888C8 + ((_i) * 4))

#define GLTSYN_TIME_H(_i)			(0x000888D8 + ((_i) * 4))

#define GLTSYN_TIME_L(_i)			(0x000888D0 + ((_i) * 4))

#define PFHH_SEM				0x000A4200 /* Reset Source: PFR */
@@ -486,9 +506,11 @@ 
#define PFTSYN_SEM_BUSY_M			BIT(0)

#define VSIQF_FD_CNT(_VSI)			(0x00464000 + ((_VSI) * 4))

#define VSIQF_FD_CNT_FD_GCNT_S			0

#define VSIQF_FD_CNT_FD_GCNT_M			ICE_M(0x3FFF, 0)

#define E800_VSIQF_FD_CNT_FD_GCNT_M		GENMASK(13, 0)

#define E830_VSIQF_FD_CNT_FD_GCNT_M		GENMASK(15, 0)

#define VSIQF_FD_CNT_FD_BCNT_S			16

#define VSIQF_FD_CNT_FD_BCNT_M			ICE_M(0x3FFF, 16)

#define E800_VSIQF_FD_CNT_FD_BCNT_M		GENMASK(29, 16)

#define E830_VSIQF_FD_CNT_FD_BCNT_M		GENMASK(31, 16)

#define VSIQF_FD_SIZE(_VSI)			(0x00462000 + ((_VSI) * 4))

#define VSIQF_HKEY_MAX_INDEX			12

#define PFPM_APM				0x000B8080
@@ -500,6 +522,10 @@ 
#define PFPM_WUS_MAG_M				BIT(1)

#define PFPM_WUS_MNG_M				BIT(3)

#define PFPM_WUS_FW_RST_WK_M			BIT(31)

#define E830_PRTMAC_CL01_PS_QNT			0x001E32A0

#define E830_PRTMAC_CL01_PS_QNT_CL0_M		GENMASK(15, 0)

#define E830_PRTMAC_CL01_QNT_THR		0x001E3320

#define E830_PRTMAC_CL01_QNT_THR_CL0_M		GENMASK(15, 0)

#define VFINT_DYN_CTLN(_i)			(0x00003800 + ((_i) * 4))

#define VFINT_DYN_CTLN_CLEARPBA_M		BIT(1)

drivers/net/ethernet/intel/ice/ice_main.c

+7 −6
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/* Copyright (c) 2018, Intel Corporation. */

/* Copyright (c) 2018-2023, Intel Corporation. */



/* Intel(R) Ethernet Connection E800 Series Linux Driver */
@@ -1748,7 +1748,7 @@ static void ice_handle_mdd_event(struct ice_pf *pf) 
		wr32(hw, GL_MDET_TX_PQM, 0xffffffff);

	}



	reg = rd32(hw, GL_MDET_TX_TCLAN);

	reg = rd32(hw, GL_MDET_TX_TCLAN_BY_MAC(hw));

	if (reg & GL_MDET_TX_TCLAN_VALID_M) {

		u8 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>

				GL_MDET_TX_TCLAN_PF_NUM_S;
@@ -1762,7 +1762,7 @@ static void ice_handle_mdd_event(struct ice_pf *pf) 
		if (netif_msg_tx_err(pf))

			dev_info(dev, "Malicious Driver Detection event %d on TX queue %d PF# %d VF# %d\n",

				 event, queue, pf_num, vf_num);

		wr32(hw, GL_MDET_TX_TCLAN, 0xffffffff);

		wr32(hw, GL_MDET_TX_TCLAN_BY_MAC(hw), U32_MAX);

	}



	reg = rd32(hw, GL_MDET_RX);
@@ -1790,9 +1790,9 @@ static void ice_handle_mdd_event(struct ice_pf *pf) 
			dev_info(dev, "Malicious Driver Detection event TX_PQM detected on PF\n");

	}



	reg = rd32(hw, PF_MDET_TX_TCLAN);

	reg = rd32(hw, PF_MDET_TX_TCLAN_BY_MAC(hw));

	if (reg & PF_MDET_TX_TCLAN_VALID_M) {

		wr32(hw, PF_MDET_TX_TCLAN, 0xFFFF);

		wr32(hw, PF_MDET_TX_TCLAN_BY_MAC(hw), 0xffff);

		if (netif_msg_tx_err(pf))

			dev_info(dev, "Malicious Driver Detection event TX_TCLAN detected on PF\n");

	}
@@ -3873,7 +3873,8 @@ static void ice_set_pf_caps(struct ice_pf *pf) 
	}



	clear_bit(ICE_FLAG_PTP_SUPPORTED, pf->flags);

	if (func_caps->common_cap.ieee_1588)

	if (func_caps->common_cap.ieee_1588 &&

	    !(pf->hw.mac_type == ICE_MAC_E830))

		set_bit(ICE_FLAG_PTP_SUPPORTED, pf->flags);



	pf->max_pf_txqs = func_caps->common_cap.num_txq;