Commit 0c19cab5 authored by Oak Zeng's avatar Oak Zeng Committed by Alex Deucher
Browse files

drm/amdgpu: HW setup of 2-level vmid0 page table 



Set up HW for 2-level vmid0 page table: 1. Set up
PAGE_TABLE_START/END registers. Currently only plan
to do 2-level page table for ALDEBARAN, so only gfxhub1.0
and mmhub1.7 is changed. 2. Set page table base register.
For 2-level page table, the page table base should point
to PDB0. 3. Disable AGP and FB aperture as they are not
used.

Signed-off-by: default avatarOak Zeng <Oak.Zeng@amd.com>
Reviewed-by: default avatarChristian Konig <christian.koenig@amd.com>
Reviewed-by: default avatarFelix Kuehling <felix.kuehling@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 522510a6

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

+42 −10
Original line number Diff line number Diff line
@@ -53,10 +53,29 @@ static void gfxhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, 


static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)

{

	uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);

	uint64_t pt_base;



	if (adev->gmc.pdb0_bo)

		pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo);

	else

		pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);



	gfxhub_v1_0_setup_vm_pt_regs(adev, 0, pt_base);



	/* If use GART for FB translation, vmid0 page table covers both

	 * vram and system memory (gart)

	 */

	if (adev->gmc.pdb0_bo) {

		WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,

				(u32)(adev->gmc.fb_start >> 12));

		WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,

				(u32)(adev->gmc.fb_start >> 44));



		WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,

				(u32)(adev->gmc.gart_end >> 12));

		WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,

				(u32)(adev->gmc.gart_end >> 44));

	} else {

		WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,

				(u32)(adev->gmc.gart_start >> 12));

		WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
@@ -67,6 +86,7 @@ static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev) 
		WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,

				(u32)(adev->gmc.gart_end >> 44));

	}

}



static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)

{
@@ -116,6 +136,18 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) 
		WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2,

			       ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);

	}



	/* In the case squeezing vram into GART aperture, we don't use

	 * FB aperture and AGP aperture. Disable them.

	 */

	if (adev->gmc.pdb0_bo) {

		WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP, 0);

		WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE, 0x00FFFFFF);

		WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0);

		WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFFFFFF);

		WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x3FFFFFFF);

		WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0);

	}

}



static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

+41 −9
Original line number Diff line number Diff line
@@ -65,10 +65,30 @@ void mmhub_v1_7_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, 


static void mmhub_v1_7_init_gart_aperture_regs(struct amdgpu_device *adev)

{

	uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);

	uint64_t pt_base;



	if (adev->gmc.pdb0_bo)

		pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo);

	else

		pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);



	mmhub_v1_7_setup_vm_pt_regs(adev, 0, pt_base);



	/* If use GART for FB translation, vmid0 page table covers both

	 * vram and system memory (gart)

	 */

	if (adev->gmc.pdb0_bo) {

		WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,

				(u32)(adev->gmc.fb_start >> 12));

		WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,

				(u32)(adev->gmc.fb_start >> 44));



		WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,

				(u32)(adev->gmc.gart_end >> 12));

		WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,

				(u32)(adev->gmc.gart_end >> 44));



	} else {

		WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,

				(u32)(adev->gmc.gart_start >> 12));

		WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
@@ -79,6 +99,7 @@ static void mmhub_v1_7_init_gart_aperture_regs(struct amdgpu_device *adev) 
		WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,

				(u32)(adev->gmc.gart_end >> 44));

	}

}



static void mmhub_v1_7_init_system_aperture_regs(struct amdgpu_device *adev)

{
@@ -97,6 +118,17 @@ static void mmhub_v1_7_init_system_aperture_regs(struct amdgpu_device *adev) 
	WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR,

		     max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);



	/* In the case squeezing vram into GART aperture, we don't use

	 * FB aperture and AGP aperture. Disable them.

	 */

	if (adev->gmc.pdb0_bo) {

		WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BOT, 0xFFFFFF);

		WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_TOP, 0);

		WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP, 0);

		WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE, 0x00FFFFFF);

		WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x3FFFFFFF);

		WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0);

	}

	if (amdgpu_sriov_vf(adev))

		return;