Commit 0c021834 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm 

Pull kvm updates from Paolo Bonzini:
 "ARM:

   - Clean up vCPU targets, always returning generic v8 as the preferred
     target

   - Trap forwarding infrastructure for nested virtualization (used for
     traps that are taken from an L2 guest and are needed by the L1
     hypervisor)

   - FEAT_TLBIRANGE support to only invalidate specific ranges of
     addresses when collapsing a table PTE to a block PTE. This avoids
     that the guest refills the TLBs again for addresses that aren't
     covered by the table PTE.

   - Fix vPMU issues related to handling of PMUver.

   - Don't unnecessary align non-stack allocations in the EL2 VA space

   - Drop HCR_VIRT_EXCP_MASK, which was never used...

   - Don't use smp_processor_id() in kvm_arch_vcpu_load(), but the cpu
     parameter instead

   - Drop redundant call to kvm_set_pfn_accessed() in user_mem_abort()

   - Remove prototypes without implementations

  RISC-V:

   - Zba, Zbs, Zicntr, Zicsr, Zifencei, and Zihpm support for guest

   - Added ONE_REG interface for SATP mode

   - Added ONE_REG interface to enable/disable multiple ISA extensions

   - Improved error codes returned by ONE_REG interfaces

   - Added KVM_GET_REG_LIST ioctl() implementation for KVM RISC-V

   - Added get-reg-list selftest for KVM RISC-V

  s390:

   - PV crypto passthrough enablement (Tony, Steffen, Viktor, Janosch)

     Allows a PV guest to use crypto cards. Card access is governed by
     the firmware and once a crypto queue is "bound" to a PV VM every
     other entity (PV or not) looses access until it is not bound
     anymore. Enablement is done via flags when creating the PV VM.

   - Guest debug fixes (Ilya)

  x86:

   - Clean up KVM's handling of Intel architectural events

   - Intel bugfixes

   - Add support for SEV-ES DebugSwap, allowing SEV-ES guests to use
     debug registers and generate/handle #DBs

   - Clean up LBR virtualization code

   - Fix a bug where KVM fails to set the target pCPU during an IRTE
     update

   - Fix fatal bugs in SEV-ES intrahost migration

   - Fix a bug where the recent (architecturally correct) change to
     reinject #BP and skip INT3 broke SEV guests (can't decode INT3 to
     skip it)

   - Retry APIC map recalculation if a vCPU is added/enabled

   - Overhaul emergency reboot code to bring SVM up to par with VMX, tie
     the "emergency disabling" behavior to KVM actually being loaded,
     and move all of the logic within KVM

   - Fix user triggerable WARNs in SVM where KVM incorrectly assumes the
     TSC ratio MSR cannot diverge from the default when TSC scaling is
     disabled up related code

   - Add a framework to allow "caching" feature flags so that KVM can
     check if the guest can use a feature without needing to search
     guest CPUID

   - Rip out the ancient MMU_DEBUG crud and replace the useful bits with
     CONFIG_KVM_PROVE_MMU

   - Fix KVM's handling of !visible guest roots to avoid premature
     triple fault injection

   - Overhaul KVM's page-track APIs, and KVMGT's usage, to reduce the
     API surface that is needed by external users (currently only
     KVMGT), and fix a variety of issues in the process

  Generic:

   - Wrap kvm_{gfn,hva}_range.pte in a union to allow mmu_notifier
     events to pass action specific data without needing to constantly
     update the main handlers.

   - Drop unused function declarations

  Selftests:

   - Add testcases to x86's sync_regs_test for detecting KVM TOCTOU bugs

   - Add support for printf() in guest code and covert all guest asserts
     to use printf-based reporting

   - Clean up the PMU event filter test and add new testcases

   - Include x86 selftests in the KVM x86 MAINTAINERS entry"

* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (279 commits)
  KVM: x86/mmu: Include mmu.h in spte.h
  KVM: x86/mmu: Use dummy root, backed by zero page, for !visible guest roots
  KVM: x86/mmu: Disallow guest from using !visible slots for page tables
  KVM: x86/mmu: Harden TDP MMU iteration against root w/o shadow page
  KVM: x86/mmu: Harden new PGD against roots without shadow pages
  KVM: x86/mmu: Add helper to convert root hpa to shadow page
  drm/i915/gvt: Drop final dependencies on KVM internal details
  KVM: x86/mmu: Handle KVM bookkeeping in page-track APIs, not callers
  KVM: x86/mmu: Drop @slot param from exported/external page-track APIs
  KVM: x86/mmu: Bug the VM if write-tracking is used but not enabled
  KVM: x86/mmu: Assert that correct locks are held for page write-tracking
  KVM: x86/mmu: Rename page-track APIs to reflect the new reality
  KVM: x86/mmu: Drop infrastructure for multiple page-track modes
  KVM: x86/mmu: Use page-track notifiers iff there are external users
  KVM: x86/mmu: Move KVM-only page-track declarations to internal header
  KVM: x86: Remove the unused page-track hook track_flush_slot()
  drm/i915/gvt: switch from ->track_flush_slot() to ->track_remove_region()
  KVM: x86: Add a new page-track hook to handle memslot deletion
  drm/i915/gvt: Don't bother removing write-protection on to-be-deleted slot
  KVM: x86: Reject memslot MOVE operations if KVMGT is attached
  ...
parents 4a0fc73d d0111516

Documentation/virt/kvm/api.rst

+3 −1
Original line number Diff line number Diff line
@@ -2259,6 +2259,8 @@ Errors: 
  EINVAL   invalid register ID, or no such register or used with VMs in

           protected virtualization mode on s390

  EPERM    (arm64) register access not allowed before vcpu finalization

  EBUSY    (riscv) changing register value not allowed after the vcpu

           has run at least once

  ======   ============================================================



(These error codes are indicative only: do not rely on a specific error
@@ -3499,7 +3501,7 @@ VCPU matching underlying host. 
---------------------



:Capability: basic

:Architectures: arm64, mips

:Architectures: arm64, mips, riscv

:Type: vcpu ioctl

:Parameters: struct kvm_reg_list (in/out)

:Returns: 0 on success; -1 on error

MAINTAINERS

+2 −0
Original line number Diff line number Diff line
@@ -11589,6 +11589,8 @@ F: arch/x86/include/uapi/asm/svm.h 
F:	arch/x86/include/uapi/asm/vmx.h

F:	arch/x86/kvm/

F:	arch/x86/kvm/*/

F:	tools/testing/selftests/kvm/*/x86_64/

F:	tools/testing/selftests/kvm/x86_64/









KERNFS









M:	Greg Kroah-Hartman <gregkh@linuxfoundation.org>
































arch/arm/include/asm/arm_pmuv3.h



+2
−0






























Original line number
Diff line number
Diff line







@@ -227,6 +227,8 @@ static inline bool kvm_set_pmuserenr(u64 val)







	return false;









}



















static inline void kvm_vcpu_pmu_resync_el0(void) {}



















/* PMU Version in DFR Register */









#define ARMV8_PMU_DFR_VER_NI        0









#define ARMV8_PMU_DFR_VER_V3P4      0x5
































arch/arm64/include/asm/kvm_arm.h



+50
−1






























Original line number
Diff line number
Diff line







@@ -18,10 +18,19 @@







#define HCR_DCT		(UL(1) << 57)









#define HCR_ATA_SHIFT	56









#define HCR_ATA		(UL(1) << HCR_ATA_SHIFT)









#define HCR_TTLBOS	(UL(1) << 55)









#define HCR_TTLBIS	(UL(1) << 54)









#define HCR_ENSCXT	(UL(1) << 53)









#define HCR_TOCU	(UL(1) << 52)









#define HCR_AMVOFFEN	(UL(1) << 51)









#define HCR_TICAB	(UL(1) << 50)









#define HCR_TID4	(UL(1) << 49)









#define HCR_FIEN	(UL(1) << 47)









#define HCR_FWB		(UL(1) << 46)









#define HCR_NV2		(UL(1) << 45)









#define HCR_AT		(UL(1) << 44)









#define HCR_NV1		(UL(1) << 43)









#define HCR_NV		(UL(1) << 42)









#define HCR_API		(UL(1) << 41)









#define HCR_APK		(UL(1) << 40)









#define HCR_TEA		(UL(1) << 37)








@@ -89,7 +98,6 @@







			 HCR_BSU_IS | HCR_FB | HCR_TACR | \









			 HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \









			 HCR_FMO | HCR_IMO | HCR_PTW | HCR_TID3)









#define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF)









#define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK | HCR_ATA)









#define HCR_HOST_NVHE_PROTECTED_FLAGS (HCR_HOST_NVHE_FLAGS | HCR_TSC)









#define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H)








@@ -324,6 +332,47 @@







				 BIT(18) |		\









				 GENMASK(16, 15))



















/*









 * FGT register definitions









 *









 * RES0 and polarity masks as of DDI0487J.a, to be updated as needed.









 * We're not using the generated masks as they are usually ahead of









 * the published ARM ARM, which we use as a reference.









 *









 * Once we get to a point where the two describe the same thing, we'll









 * merge the definitions. One day.









 */









#define __HFGRTR_EL2_RES0	(GENMASK(63, 56) | GENMASK(53, 51))









#define __HFGRTR_EL2_MASK	GENMASK(49, 0)









#define __HFGRTR_EL2_nMASK	(GENMASK(55, 54) | BIT(50))



















#define __HFGWTR_EL2_RES0	(GENMASK(63, 56) | GENMASK(53, 51) |	\









				 BIT(46) | BIT(42) | BIT(40) | BIT(28) | \









				 GENMASK(26, 25) | BIT(21) | BIT(18) |	\









				 GENMASK(15, 14) | GENMASK(10, 9) | BIT(2))









#define __HFGWTR_EL2_MASK	GENMASK(49, 0)









#define __HFGWTR_EL2_nMASK	(GENMASK(55, 54) | BIT(50))



















#define __HFGITR_EL2_RES0	GENMASK(63, 57)









#define __HFGITR_EL2_MASK	GENMASK(54, 0)









#define __HFGITR_EL2_nMASK	GENMASK(56, 55)



















#define __HDFGRTR_EL2_RES0	(BIT(49) | BIT(42) | GENMASK(39, 38) |	\









				 GENMASK(21, 20) | BIT(8))









#define __HDFGRTR_EL2_MASK	~__HDFGRTR_EL2_nMASK









#define __HDFGRTR_EL2_nMASK	GENMASK(62, 59)



















#define __HDFGWTR_EL2_RES0	(BIT(63) | GENMASK(59, 58) | BIT(51) | BIT(47) | \









				 BIT(43) | GENMASK(40, 38) | BIT(34) | BIT(30) | \









				 BIT(22) | BIT(9) | BIT(6))









#define __HDFGWTR_EL2_MASK	~__HDFGWTR_EL2_nMASK









#define __HDFGWTR_EL2_nMASK	GENMASK(62, 60)



















/* Similar definitions for HCRX_EL2 */









#define __HCRX_EL2_RES0		(GENMASK(63, 16) | GENMASK(13, 12))









#define __HCRX_EL2_MASK		(0)









#define __HCRX_EL2_nMASK	(GENMASK(15, 14) | GENMASK(4, 0))



















/* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */









#define HPFAR_MASK	(~UL(0xf))









/*
































arch/arm64/include/asm/kvm_asm.h



+3
−0






























Original line number
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@@ -70,6 +70,7 @@ enum __kvm_host_smccc_func {







	__KVM_HOST_SMCCC_FUNC___kvm_tlb_flush_vmid_ipa,









	__KVM_HOST_SMCCC_FUNC___kvm_tlb_flush_vmid_ipa_nsh,









	__KVM_HOST_SMCCC_FUNC___kvm_tlb_flush_vmid,









	__KVM_HOST_SMCCC_FUNC___kvm_tlb_flush_vmid_range,









	__KVM_HOST_SMCCC_FUNC___kvm_flush_cpu_context,









	__KVM_HOST_SMCCC_FUNC___kvm_timer_set_cntvoff,









	__KVM_HOST_SMCCC_FUNC___vgic_v3_read_vmcr,








@@ -229,6 +230,8 @@ extern void __kvm_tlb_flush_vmid_ipa(struct kvm_s2_mmu *mmu, phys_addr_t ipa,







extern void __kvm_tlb_flush_vmid_ipa_nsh(struct kvm_s2_mmu *mmu,









					 phys_addr_t ipa,









					 int level);









extern void __kvm_tlb_flush_vmid_range(struct kvm_s2_mmu *mmu,









					phys_addr_t start, unsigned long pages);









extern void __kvm_tlb_flush_vmid(struct kvm_s2_mmu *mmu);



















extern void __kvm_timer_set_cntvoff(u64 cntvoff);