Commit 0be3df18 authored by Jon Lin's avatar Jon Lin Committed by Heiko Stuebner
Browse files

clk: rockchip: rk3036: fix up the sclk_sfc parent error 



Choose the correct pll

Signed-off-by: default avatarElaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: default avatarJon Lin <jon.lin@rock-chips.com>
Acked-by: default avatarStephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20210713094456.23288-5-jon.lin@rock-chips.com


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent b13c1fff

drivers/clk/rockchip/clk-rk3036.c

+2 −1
Original line number Diff line number Diff line
@@ -121,6 +121,7 @@ PNAME(mux_pll_src_3plls_p) = { "apll", "dpll", "gpll" }; 
PNAME(mux_timer_p)		= { "xin24m", "pclk_peri_src" };



PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p)	= { "apll", "dpll", "gpll", "usb480m" };

PNAME(mux_pll_src_dmyapll_dpll_gpll_xin24_p)   = { "dummy_apll", "dpll", "gpll", "xin24m" };



PNAME(mux_mmc_src_p)	= { "apll", "dpll", "gpll", "xin24m" };

PNAME(mux_i2s_pre_p)	= { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
@@ -340,7 +341,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { 
			RK2928_CLKSEL_CON(16), 8, 2, MFLAGS, 10, 5, DFLAGS,

			RK2928_CLKGATE_CON(10), 4, GFLAGS),



	COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_apll_dpll_gpll_usb480m_p, 0,

	COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_dmyapll_dpll_gpll_xin24_p, 0,

			RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS,

			RK2928_CLKGATE_CON(10), 5, GFLAGS),