Commit 0ba2661d authored by Imre Deak's avatar Imre Deak
Browse files

drm/i915: Rename the power domain names to end with pipes/ports 



Make all power domain names end with the pipe/port instance for
consistency.

No functional changes.

Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarJouni Högander <jouni.hogander@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220414210657.1785773-6-imre.deak@intel.com
parent 6a006ee9

drivers/gpu/drm/i915/display/icl_dsi.c

+4 −4
Original line number Diff line number Diff line
@@ -399,8 +399,8 @@ static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv, 
		intel_dsi->io_wakeref[port] =

			intel_display_power_get(dev_priv,

						port == PORT_A ?

						POWER_DOMAIN_PORT_DDI_A_IO :

						POWER_DOMAIN_PORT_DDI_B_IO);

						POWER_DOMAIN_PORT_DDI_IO_A :

						POWER_DOMAIN_PORT_DDI_IO_B);

	}

}
@@ -1425,8 +1425,8 @@ static void gen11_dsi_disable_io_power(struct intel_encoder *encoder) 
		wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]);

		intel_display_power_put(dev_priv,

					port == PORT_A ?

					POWER_DOMAIN_PORT_DDI_A_IO :

					POWER_DOMAIN_PORT_DDI_B_IO,

					POWER_DOMAIN_PORT_DDI_IO_A :

					POWER_DOMAIN_PORT_DDI_IO_B,

					wakeref);

	}

drivers/gpu/drm/i915/display/intel_ddi.c

+1 −1
Original line number Diff line number Diff line
@@ -4492,7 +4492,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 
	}



	drm_WARN_ON(&dev_priv->drm, port > PORT_I);

	dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO +

	dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_IO_A +

					      port - PORT_A;



	if (init_dp) {

drivers/gpu/drm/i915/display/intel_display.c

+17 −17
Original line number Diff line number Diff line
@@ -2161,23 +2161,23 @@ enum intel_display_power_domain intel_port_to_power_domain(enum port port) 
{

	switch (port) {

	case PORT_A:

		return POWER_DOMAIN_PORT_DDI_A_LANES;

		return POWER_DOMAIN_PORT_DDI_LANES_A;

	case PORT_B:

		return POWER_DOMAIN_PORT_DDI_B_LANES;

		return POWER_DOMAIN_PORT_DDI_LANES_B;

	case PORT_C:

		return POWER_DOMAIN_PORT_DDI_C_LANES;

		return POWER_DOMAIN_PORT_DDI_LANES_C;

	case PORT_D:

		return POWER_DOMAIN_PORT_DDI_D_LANES;

		return POWER_DOMAIN_PORT_DDI_LANES_D;

	case PORT_E:

		return POWER_DOMAIN_PORT_DDI_E_LANES;

		return POWER_DOMAIN_PORT_DDI_LANES_E;

	case PORT_F:

		return POWER_DOMAIN_PORT_DDI_F_LANES;

		return POWER_DOMAIN_PORT_DDI_LANES_F;

	case PORT_G:

		return POWER_DOMAIN_PORT_DDI_G_LANES;

		return POWER_DOMAIN_PORT_DDI_LANES_G;

	case PORT_H:

		return POWER_DOMAIN_PORT_DDI_H_LANES;

		return POWER_DOMAIN_PORT_DDI_LANES_H;

	case PORT_I:

		return POWER_DOMAIN_PORT_DDI_I_LANES;

		return POWER_DOMAIN_PORT_DDI_LANES_I;

	default:

		MISSING_CASE(port);

		return POWER_DOMAIN_PORT_OTHER;
@@ -2190,22 +2190,22 @@ intel_aux_power_domain(struct intel_digital_port *dig_port) 
	if (intel_tc_port_in_tbt_alt_mode(dig_port)) {

		switch (dig_port->aux_ch) {

		case AUX_CH_C:

			return POWER_DOMAIN_AUX_C_TBT;

			return POWER_DOMAIN_AUX_TBT_C;

		case AUX_CH_D:

			return POWER_DOMAIN_AUX_D_TBT;

			return POWER_DOMAIN_AUX_TBT_D;

		case AUX_CH_E:

			return POWER_DOMAIN_AUX_E_TBT;

			return POWER_DOMAIN_AUX_TBT_E;

		case AUX_CH_F:

			return POWER_DOMAIN_AUX_F_TBT;

			return POWER_DOMAIN_AUX_TBT_F;

		case AUX_CH_G:

			return POWER_DOMAIN_AUX_G_TBT;

			return POWER_DOMAIN_AUX_TBT_G;

		case AUX_CH_H:

			return POWER_DOMAIN_AUX_H_TBT;

			return POWER_DOMAIN_AUX_TBT_H;

		case AUX_CH_I:

			return POWER_DOMAIN_AUX_I_TBT;

			return POWER_DOMAIN_AUX_TBT_I;

		default:

			MISSING_CASE(dig_port->aux_ch);

			return POWER_DOMAIN_AUX_C_TBT;

			return POWER_DOMAIN_AUX_TBT_C;

		}

	}

drivers/gpu/drm/i915/display/intel_display_power.c

+58 −58
Original line number Diff line number Diff line
@@ -44,14 +44,14 @@ intel_display_power_domain_str(enum intel_display_power_domain domain) 
		return "PIPE_C";

	case POWER_DOMAIN_PIPE_D:

		return "PIPE_D";

	case POWER_DOMAIN_PIPE_A_PANEL_FITTER:

		return "PIPE_A_PANEL_FITTER";

	case POWER_DOMAIN_PIPE_B_PANEL_FITTER:

		return "PIPE_B_PANEL_FITTER";

	case POWER_DOMAIN_PIPE_C_PANEL_FITTER:

		return "PIPE_C_PANEL_FITTER";

	case POWER_DOMAIN_PIPE_D_PANEL_FITTER:

		return "PIPE_D_PANEL_FITTER";

	case POWER_DOMAIN_PIPE_PANEL_FITTER_A:

		return "PIPE_PANEL_FITTER_A";

	case POWER_DOMAIN_PIPE_PANEL_FITTER_B:

		return "PIPE_PANEL_FITTER_B";

	case POWER_DOMAIN_PIPE_PANEL_FITTER_C:

		return "PIPE_PANEL_FITTER_C";

	case POWER_DOMAIN_PIPE_PANEL_FITTER_D:

		return "PIPE_PANEL_FITTER_D";

	case POWER_DOMAIN_TRANSCODER_A:

		return "TRANSCODER_A";

	case POWER_DOMAIN_TRANSCODER_B:
@@ -68,42 +68,42 @@ intel_display_power_domain_str(enum intel_display_power_domain domain) 
		return "TRANSCODER_DSI_C";

	case POWER_DOMAIN_TRANSCODER_VDSC_PW2:

		return "TRANSCODER_VDSC_PW2";

	case POWER_DOMAIN_PORT_DDI_A_LANES:

		return "PORT_DDI_A_LANES";

	case POWER_DOMAIN_PORT_DDI_B_LANES:

		return "PORT_DDI_B_LANES";

	case POWER_DOMAIN_PORT_DDI_C_LANES:

		return "PORT_DDI_C_LANES";

	case POWER_DOMAIN_PORT_DDI_D_LANES:

		return "PORT_DDI_D_LANES";

	case POWER_DOMAIN_PORT_DDI_E_LANES:

		return "PORT_DDI_E_LANES";

	case POWER_DOMAIN_PORT_DDI_F_LANES:

		return "PORT_DDI_F_LANES";

	case POWER_DOMAIN_PORT_DDI_G_LANES:

		return "PORT_DDI_G_LANES";

	case POWER_DOMAIN_PORT_DDI_H_LANES:

		return "PORT_DDI_H_LANES";

	case POWER_DOMAIN_PORT_DDI_I_LANES:

		return "PORT_DDI_I_LANES";

	case POWER_DOMAIN_PORT_DDI_A_IO:

		return "PORT_DDI_A_IO";

	case POWER_DOMAIN_PORT_DDI_B_IO:

		return "PORT_DDI_B_IO";

	case POWER_DOMAIN_PORT_DDI_C_IO:

		return "PORT_DDI_C_IO";

	case POWER_DOMAIN_PORT_DDI_D_IO:

		return "PORT_DDI_D_IO";

	case POWER_DOMAIN_PORT_DDI_E_IO:

		return "PORT_DDI_E_IO";

	case POWER_DOMAIN_PORT_DDI_F_IO:

		return "PORT_DDI_F_IO";

	case POWER_DOMAIN_PORT_DDI_G_IO:

		return "PORT_DDI_G_IO";

	case POWER_DOMAIN_PORT_DDI_H_IO:

		return "PORT_DDI_H_IO";

	case POWER_DOMAIN_PORT_DDI_I_IO:

		return "PORT_DDI_I_IO";

	case POWER_DOMAIN_PORT_DDI_LANES_A:

		return "PORT_DDI_LANES_A";

	case POWER_DOMAIN_PORT_DDI_LANES_B:

		return "PORT_DDI_LANES_B";

	case POWER_DOMAIN_PORT_DDI_LANES_C:

		return "PORT_DDI_LANES_C";

	case POWER_DOMAIN_PORT_DDI_LANES_D:

		return "PORT_DDI_LANES_D";

	case POWER_DOMAIN_PORT_DDI_LANES_E:

		return "PORT_DDI_LANES_E";

	case POWER_DOMAIN_PORT_DDI_LANES_F:

		return "PORT_DDI_LANES_F";

	case POWER_DOMAIN_PORT_DDI_LANES_G:

		return "PORT_DDI_LANES_G";

	case POWER_DOMAIN_PORT_DDI_LANES_H:

		return "PORT_DDI_LANES_H";

	case POWER_DOMAIN_PORT_DDI_LANES_I:

		return "PORT_DDI_LANES_I";

	case POWER_DOMAIN_PORT_DDI_IO_A:

		return "PORT_DDI_IO_A";

	case POWER_DOMAIN_PORT_DDI_IO_B:

		return "PORT_DDI_IO_B";

	case POWER_DOMAIN_PORT_DDI_IO_C:

		return "PORT_DDI_IO_C";

	case POWER_DOMAIN_PORT_DDI_IO_D:

		return "PORT_DDI_IO_D";

	case POWER_DOMAIN_PORT_DDI_IO_E:

		return "PORT_DDI_IO_E";

	case POWER_DOMAIN_PORT_DDI_IO_F:

		return "PORT_DDI_IO_F";

	case POWER_DOMAIN_PORT_DDI_IO_G:

		return "PORT_DDI_IO_G";

	case POWER_DOMAIN_PORT_DDI_IO_H:

		return "PORT_DDI_IO_H";

	case POWER_DOMAIN_PORT_DDI_IO_I:

		return "PORT_DDI_IO_I";

	case POWER_DOMAIN_PORT_DSI:

		return "PORT_DSI";

	case POWER_DOMAIN_PORT_CRT:
@@ -136,20 +136,20 @@ intel_display_power_domain_str(enum intel_display_power_domain domain) 
		return "AUX_I";

	case POWER_DOMAIN_AUX_IO_A:

		return "AUX_IO_A";

	case POWER_DOMAIN_AUX_C_TBT:

		return "AUX_C_TBT";

	case POWER_DOMAIN_AUX_D_TBT:

		return "AUX_D_TBT";

	case POWER_DOMAIN_AUX_E_TBT:

		return "AUX_E_TBT";

	case POWER_DOMAIN_AUX_F_TBT:

		return "AUX_F_TBT";

	case POWER_DOMAIN_AUX_G_TBT:

		return "AUX_G_TBT";

	case POWER_DOMAIN_AUX_H_TBT:

		return "AUX_H_TBT";

	case POWER_DOMAIN_AUX_I_TBT:

		return "AUX_I_TBT";

	case POWER_DOMAIN_AUX_TBT_C:

		return "AUX_TBT_C";

	case POWER_DOMAIN_AUX_TBT_D:

		return "AUX_TBT_D";

	case POWER_DOMAIN_AUX_TBT_E:

		return "AUX_TBT_E";

	case POWER_DOMAIN_AUX_TBT_F:

		return "AUX_TBT_F";

	case POWER_DOMAIN_AUX_TBT_G:

		return "AUX_TBT_G";

	case POWER_DOMAIN_AUX_TBT_H:

		return "AUX_TBT_H";

	case POWER_DOMAIN_AUX_TBT_I:

		return "AUX_TBT_I";

	case POWER_DOMAIN_GMBUS:

		return "GMBUS";

	case POWER_DOMAIN_INIT:

drivers/gpu/drm/i915/display/intel_display_power.h

+36 −36
Original line number Diff line number Diff line
@@ -25,10 +25,10 @@ enum intel_display_power_domain { 
	POWER_DOMAIN_PIPE_B,

	POWER_DOMAIN_PIPE_C,

	POWER_DOMAIN_PIPE_D,

	POWER_DOMAIN_PIPE_A_PANEL_FITTER,

	POWER_DOMAIN_PIPE_B_PANEL_FITTER,

	POWER_DOMAIN_PIPE_C_PANEL_FITTER,

	POWER_DOMAIN_PIPE_D_PANEL_FITTER,

	POWER_DOMAIN_PIPE_PANEL_FITTER_A,

	POWER_DOMAIN_PIPE_PANEL_FITTER_B,

	POWER_DOMAIN_PIPE_PANEL_FITTER_C,

	POWER_DOMAIN_PIPE_PANEL_FITTER_D,

	POWER_DOMAIN_TRANSCODER_A,

	POWER_DOMAIN_TRANSCODER_B,

	POWER_DOMAIN_TRANSCODER_C,
@@ -40,17 +40,17 @@ enum intel_display_power_domain { 
	/* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */

	POWER_DOMAIN_TRANSCODER_VDSC_PW2,



	POWER_DOMAIN_PORT_DDI_A_LANES,

	POWER_DOMAIN_PORT_DDI_B_LANES,

	POWER_DOMAIN_PORT_DDI_C_LANES,

	POWER_DOMAIN_PORT_DDI_D_LANES,

	POWER_DOMAIN_PORT_DDI_E_LANES,

	POWER_DOMAIN_PORT_DDI_F_LANES,

	POWER_DOMAIN_PORT_DDI_G_LANES,

	POWER_DOMAIN_PORT_DDI_H_LANES,

	POWER_DOMAIN_PORT_DDI_I_LANES,



	POWER_DOMAIN_PORT_DDI_LANES_TC1 = POWER_DOMAIN_PORT_DDI_D_LANES, /* tgl+ */

	POWER_DOMAIN_PORT_DDI_LANES_A,

	POWER_DOMAIN_PORT_DDI_LANES_B,

	POWER_DOMAIN_PORT_DDI_LANES_C,

	POWER_DOMAIN_PORT_DDI_LANES_D,

	POWER_DOMAIN_PORT_DDI_LANES_E,

	POWER_DOMAIN_PORT_DDI_LANES_F,

	POWER_DOMAIN_PORT_DDI_LANES_G,

	POWER_DOMAIN_PORT_DDI_LANES_H,

	POWER_DOMAIN_PORT_DDI_LANES_I,



	POWER_DOMAIN_PORT_DDI_LANES_TC1 = POWER_DOMAIN_PORT_DDI_LANES_D, /* tgl+ */

	POWER_DOMAIN_PORT_DDI_LANES_TC2,

	POWER_DOMAIN_PORT_DDI_LANES_TC3,

	POWER_DOMAIN_PORT_DDI_LANES_TC4,
@@ -60,17 +60,17 @@ enum intel_display_power_domain { 
	POWER_DOMAIN_PORT_DDI_LANES_D_XELPD = POWER_DOMAIN_PORT_DDI_LANES_TC5, /* XELPD */

	POWER_DOMAIN_PORT_DDI_LANES_E_XELPD,



	POWER_DOMAIN_PORT_DDI_A_IO,

	POWER_DOMAIN_PORT_DDI_B_IO,

	POWER_DOMAIN_PORT_DDI_C_IO,

	POWER_DOMAIN_PORT_DDI_D_IO,

	POWER_DOMAIN_PORT_DDI_E_IO,

	POWER_DOMAIN_PORT_DDI_F_IO,

	POWER_DOMAIN_PORT_DDI_G_IO,

	POWER_DOMAIN_PORT_DDI_H_IO,

	POWER_DOMAIN_PORT_DDI_I_IO,



	POWER_DOMAIN_PORT_DDI_IO_TC1 = POWER_DOMAIN_PORT_DDI_D_IO, /* tgl+ */

	POWER_DOMAIN_PORT_DDI_IO_A,

	POWER_DOMAIN_PORT_DDI_IO_B,

	POWER_DOMAIN_PORT_DDI_IO_C,

	POWER_DOMAIN_PORT_DDI_IO_D,

	POWER_DOMAIN_PORT_DDI_IO_E,

	POWER_DOMAIN_PORT_DDI_IO_F,

	POWER_DOMAIN_PORT_DDI_IO_G,

	POWER_DOMAIN_PORT_DDI_IO_H,

	POWER_DOMAIN_PORT_DDI_IO_I,



	POWER_DOMAIN_PORT_DDI_IO_TC1 = POWER_DOMAIN_PORT_DDI_IO_D, /* tgl+ */

	POWER_DOMAIN_PORT_DDI_IO_TC2,

	POWER_DOMAIN_PORT_DDI_IO_TC3,

	POWER_DOMAIN_PORT_DDI_IO_TC4,
@@ -107,15 +107,15 @@ enum intel_display_power_domain { 
	POWER_DOMAIN_AUX_E_XELPD,



	POWER_DOMAIN_AUX_IO_A,

	POWER_DOMAIN_AUX_C_TBT,

	POWER_DOMAIN_AUX_D_TBT,

	POWER_DOMAIN_AUX_E_TBT,

	POWER_DOMAIN_AUX_F_TBT,

	POWER_DOMAIN_AUX_G_TBT,

	POWER_DOMAIN_AUX_H_TBT,

	POWER_DOMAIN_AUX_I_TBT,



	POWER_DOMAIN_AUX_TBT1 = POWER_DOMAIN_AUX_D_TBT, /* tgl+ */

	POWER_DOMAIN_AUX_TBT_C,

	POWER_DOMAIN_AUX_TBT_D,

	POWER_DOMAIN_AUX_TBT_E,

	POWER_DOMAIN_AUX_TBT_F,

	POWER_DOMAIN_AUX_TBT_G,

	POWER_DOMAIN_AUX_TBT_H,

	POWER_DOMAIN_AUX_TBT_I,



	POWER_DOMAIN_AUX_TBT1 = POWER_DOMAIN_AUX_TBT_D, /* tgl+ */

	POWER_DOMAIN_AUX_TBT2,

	POWER_DOMAIN_AUX_TBT3,

	POWER_DOMAIN_AUX_TBT4,
@@ -134,7 +134,7 @@ enum intel_display_power_domain { 


#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)

#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \

		((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)

		((pipe) + POWER_DOMAIN_PIPE_PANEL_FITTER_A)

#define POWER_DOMAIN_TRANSCODER(tran) \

	((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \

	 (tran) + POWER_DOMAIN_TRANSCODER_A)