Commit 0b774629 authored by Jing Liu's avatar Jing Liu Committed by Paolo Bonzini
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KVM: x86: expose AVX512_BF16 feature to guest 

AVX512 BFLOAT16 instructions support 16-bit BFLOAT16 floating-point
format (BF16) for deep learning optimization.

Intel adds AVX512 BFLOAT16 feature in CooperLake, which is CPUID.7.1.EAX[5].

Detailed information of the CPUID bit can be found here,
https://software.intel.com/sites/default/files/managed/c5/15/\


architecture-instruction-set-extensions-programming-reference.pdf.

Signed-off-by: default avatarJing Liu <jing2.liu@linux.intel.com>
[Fix type mismatch in min, changing constant "1" to "1u". - Paolo]
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent 964a4eac

arch/x86/kvm/cpuid.c

+11 −1
Original line number Diff line number Diff line
@@ -368,9 +368,13 @@ static inline void do_cpuid_7_mask(struct kvm_cpuid_entry2 *entry, int index) 
		F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |

		F(MD_CLEAR);



	/* cpuid 7.1.eax */

	const u32 kvm_cpuid_7_1_eax_x86_features =

		F(AVX512_BF16);



	switch (index) {

	case 0:

		entry->eax = 0;

		entry->eax = min(entry->eax, 1u);

		entry->ebx &= kvm_cpuid_7_0_ebx_x86_features;

		cpuid_mask(&entry->ebx, CPUID_7_0_EBX);

		/* TSC_ADJUST is emulated */
@@ -394,6 +398,12 @@ static inline void do_cpuid_7_mask(struct kvm_cpuid_entry2 *entry, int index) 
		 */

		entry->edx |= F(ARCH_CAPABILITIES);

		break;

	case 1:

		entry->eax &= kvm_cpuid_7_1_eax_x86_features;

		entry->ebx = 0;

		entry->ecx = 0;

		entry->edx = 0;

		break;

	default:

		WARN_ON_ONCE(1);

		entry->eax = 0;