Commit 0b6e362b authored by leoliuoc's avatar leoliuoc
Browse files

update pmu for Zhaoxin CPUs 

zhaoxin inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I5SRF7


CVE: NA

--------------------------------------------

Adds support for more Zhaoxin processors. And improve the uncore code to
provide more functions and support.

Signed-off-by: default avatarleoliuoc <leoliu-oc@zhaoxin.com>
parent ca3b6b0e

arch/x86/events/zhaoxin/core.c

+21 −6
Original line number Diff line number Diff line
@@ -28,6 +28,8 @@ static u64 zx_pmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = { 
	[PERF_COUNT_HW_CACHE_REFERENCES]  = 0x0515,

	[PERF_COUNT_HW_CACHE_MISSES]      = 0x051a,

	[PERF_COUNT_HW_BUS_CYCLES]        = 0x0083,

	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x0028,

	[PERF_COUNT_HW_BRANCH_MISSES] = 0x0029,

};



static struct event_constraint zxc_event_constraints[] __read_mostly = {
@@ -511,7 +513,7 @@ __init int zhaoxin_pmu_init(void) 
	unsigned int unused;

	int version;



	pr_info("Welcome to zhaoxin pmu!\n");

	pr_info("Welcome to pmu!\n");



	/*

	 * Check whether the Architectural PerfMon supports
@@ -553,6 +555,8 @@ __init int zhaoxin_pmu_init(void) 
			zx_pmon_event_map[PERF_COUNT_HW_CACHE_REFERENCES] = 0;

			zx_pmon_event_map[PERF_COUNT_HW_CACHE_MISSES] = 0;

			zx_pmon_event_map[PERF_COUNT_HW_BUS_CYCLES] = 0;

			zx_pmon_event_map[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0;

			zx_pmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0;



			pr_cont("ZXC events, ");

			break;
@@ -584,11 +588,22 @@ __init int zhaoxin_pmu_init(void) 


			x86_pmu.event_constraints = zxd_event_constraints;



			zx_pmon_event_map[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x0028;

			zx_pmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x0029;



			pr_cont("ZXE events, ");

			break;

		case 0x5b:



			zx_pmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =

			X86_CONFIG(.event = 0x02, .umask = 0x01, .inv = 0x01, .cmask = 0x01);



			memcpy(hw_cache_event_ids, zxe_hw_cache_event_ids,

					sizeof(hw_cache_event_ids));



			x86_pmu.event_constraints = zxd_event_constraints;

			zx_pmon_event_map[PERF_COUNT_HW_CACHE_REFERENCES]  = 0x051a;

			zx_pmon_event_map[PERF_COUNT_HW_CACHE_MISSES]      = 0;



			pr_cont("CNX events, ");

			break;

		default:

			return -ENODEV;

		}

arch/x86/events/zhaoxin/uncore.c

+1384 −255

File changed.

Preview size limit exceeded, changes collapsed.

arch/x86/events/zhaoxin/uncore.h

+72 −27
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Zhaoxin PMU; like Intel Architectural PerfMon-v2

 */

#include <linux/slab.h>

#include <linux/pci.h>

#include <asm/apicdef.h>
@@ -10,13 +7,12 @@ 
#include <linux/perf_event.h>

#include "../perf_event.h"



#define ZHAOXIN_FAM7_ZXD		0x1b

#define ZHAOXIN_FAM7_ZXE		0x3b

#define ZHAOXIN_FAM7_WUDAOKOU		0x1b

#define ZHAOXIN_FAM7_LUJIAZUI		0x3b

#define ZHAOXIN_FAM7_YONGFENG		0x5b



#define UNCORE_PMU_NAME_LEN		32

#define UNCORE_PMU_HRTIMER_INTERVAL	(60LL * NSEC_PER_SEC)

#define UNCORE_CHX_IMC_HRTIMER_INTERVAL (5ULL * NSEC_PER_SEC)





#define UNCORE_FIXED_EVENT              0xff

#define UNCORE_PMC_IDX_MAX_GENERIC      4
@@ -25,6 +21,10 @@ 


#define UNCORE_PMC_IDX_MAX              (UNCORE_PMC_IDX_FIXED + 1)



#define UNCORE_PCI_DEV_DATA(type, idx)  ((type << 8) | idx)

#define UNCORE_PCI_DEV_TYPE(data)       ((data >> 8) & 0xff)

#define UNCORE_PCI_DEV_IDX(data)        (data & 0xff)



struct zhaoxin_uncore_ops;

struct zhaoxin_uncore_pmu;

struct zhaoxin_uncore_box;
@@ -62,17 +62,17 @@ struct zhaoxin_uncore_type { 
#define events_group attr_groups[2]



struct zhaoxin_uncore_ops {

	void (*init_box)(struct zhaoxin_uncore_box *);

	void (*exit_box)(struct zhaoxin_uncore_box *);

	void (*disable_box)(struct zhaoxin_uncore_box *);

	void (*enable_box)(struct zhaoxin_uncore_box *);

	void (*disable_event)(struct zhaoxin_uncore_box *, struct perf_event *);

	void (*enable_event)(struct zhaoxin_uncore_box *, struct perf_event *);

	u64 (*read_counter)(struct zhaoxin_uncore_box *, struct perf_event *);

	int (*hw_config)(struct zhaoxin_uncore_box *, struct perf_event *);

	struct event_constraint *(*get_constraint)(struct zhaoxin_uncore_box *,

						   struct perf_event *);

	void (*put_constraint)(struct zhaoxin_uncore_box *, struct perf_event *);

	void (*init_box)(struct zhaoxin_uncore_box *box);

	void (*exit_box)(struct zhaoxin_uncore_box *box);

	void (*disable_box)(struct zhaoxin_uncore_box *box);

	void (*enable_box)(struct zhaoxin_uncore_box *box);

	void (*disable_event)(struct zhaoxin_uncore_box *box, struct perf_event *event);

	void (*enable_event)(struct zhaoxin_uncore_box *box, struct perf_event *event);

	u64 (*read_counter)(struct zhaoxin_uncore_box *box, struct perf_event *event);

	int (*hw_config)(struct zhaoxin_uncore_box *box, struct perf_event *event);

	struct event_constraint *(*get_constraint)(struct zhaoxin_uncore_box *box,

						   struct perf_event *event);

	void (*put_constraint)(struct zhaoxin_uncore_box *box, struct perf_event *event);

};



struct zhaoxin_uncore_pmu {
@@ -95,6 +95,8 @@ struct zhaoxin_uncore_extra_reg { 
struct zhaoxin_uncore_box {

	int pci_phys_id;

	int package_id;	/*Package ID */

	int cluster_id;

	int subnode_id;

	int n_active;	/* number of active events */

	int n_events;

	int cpu;	/* cpu to collect events */
@@ -122,6 +124,11 @@ struct uncore_event_desc { 
	const char *config;

};



struct hw_info {

	u64 config_info;

	u64 active_state;

};



ssize_t zx_uncore_event_show(struct device *dev,

			  struct device_attribute *attr, char *buf);
@@ -147,6 +154,33 @@ static inline bool uncore_pmc_fixed(int idx) 
	return idx == UNCORE_PMC_IDX_FIXED;

}



static inline unsigned int uncore_pci_box_ctl(struct zhaoxin_uncore_box *box)

{

	return box->pmu->type->box_ctl;

}



static inline unsigned int uncore_pci_fixed_ctl(struct zhaoxin_uncore_box *box)

{

	return box->pmu->type->fixed_ctl;

}



static inline unsigned int uncore_pci_fixed_ctr(struct zhaoxin_uncore_box *box)

{

	return box->pmu->type->fixed_ctr;

}



static inline

unsigned int uncore_pci_event_ctl(struct zhaoxin_uncore_box *box, int idx)

{

	return idx * 4 + box->pmu->type->event_ctl;

}



static inline

unsigned int uncore_pci_perf_ctr(struct zhaoxin_uncore_box *box, int idx)

{

	return idx * 8 + box->pmu->type->perf_ctr;

}



static inline unsigned int uncore_msr_box_offset(struct zhaoxin_uncore_box *box)

{

	struct zhaoxin_uncore_pmu *pmu = box->pmu;
@@ -194,24 +228,34 @@ unsigned int uncore_msr_perf_ctr(struct zhaoxin_uncore_box *box, int idx) 
static inline

unsigned int uncore_fixed_ctl(struct zhaoxin_uncore_box *box)

{

	if (box->pci_dev)

		return uncore_pci_fixed_ctl(box);

	else

		return uncore_msr_fixed_ctl(box);

}



static inline

unsigned int uncore_fixed_ctr(struct zhaoxin_uncore_box *box)

{

	if (box->pci_dev)

		return uncore_pci_fixed_ctr(box);

	else

		return uncore_msr_fixed_ctr(box);

}



static inline

unsigned int uncore_event_ctl(struct zhaoxin_uncore_box *box, int idx)

{

{	if (box->pci_dev)

		return uncore_pci_event_ctl(box, idx);

	else

		return uncore_msr_event_ctl(box, idx);

}



static inline

unsigned int uncore_perf_ctr(struct zhaoxin_uncore_box *box, int idx)

{

{	if (box->pci_dev)

		return uncore_pci_perf_ctr(box, idx);

	else

		return uncore_msr_perf_ctr(box, idx);

}
@@ -291,7 +335,6 @@ static inline struct zhaoxin_uncore_box *uncore_event_to_box(struct perf_event * 
	return event->pmu_private;

}





static struct zhaoxin_uncore_box *uncore_pmu_to_box(struct zhaoxin_uncore_pmu *pmu, int cpu);

static u64 uncore_msr_read_counter(struct zhaoxin_uncore_box *box, struct perf_event *event);
@@ -308,4 +351,6 @@ uncore_get_constraint(struct zhaoxin_uncore_box *box, struct perf_event *event); 
void uncore_put_constraint(struct zhaoxin_uncore_box *box, struct perf_event *event);

u64 uncore_shared_reg_config(struct zhaoxin_uncore_box *box, int idx);



void chx_uncore_cpu_init(void);
 
void wudaokou_uncore_cpu_init(void);

void yongfeng_uncore_cpu_init(void);

int yongfeng_uncore_pci_init(void);