Commit 0b6d70e5 authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

Merge tag 'irqchip-5.12' of... 

Merge tag 'irqchip-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core

Pull irqchip updates from Marc Zyngier

 - New driver for the MIPS-based Realtek RTL838x/RTL839x SoC
 - Conversion of the sun6i-r support code to a hierarchical setup
 - Fix wake-up interrupts for the ls-extirq driver
 - Fix MSI allocation for the loongson-pch-msi driver
 - Add compatible strings for new Qualcomm SoCs
 - Tidy up a few Kconfig entries (IMX, CSKY)
 - Spelling phyksiz
 - Remove the sirfsoc and tango drivers

Link: https://lore.kernel.org/r/20210214124015.3333457-1-maz@kernel.org
parents c2609541 a890caeb

Documentation/devicetree/bindings/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml

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# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Allwinner A31 NMI/Wakeup Interrupt Controller Device Tree Bindings



maintainers:

  - Chen-Yu Tsai <wens@csie.org>

  - Maxime Ripard <mripard@kernel.org>



allOf:

  - $ref: /schemas/interrupt-controller.yaml#



properties:

  "#interrupt-cells":

    const: 3

    description:

      The first cell is GIC_SPI (0), the second cell is the IRQ number, and

      the third cell is the trigger type as defined in interrupt.txt in this

      directory.



  compatible:

    oneOf:

      - const: allwinner,sun6i-a31-r-intc

      - items:

          - enum:

              - allwinner,sun8i-a83t-r-intc

              - allwinner,sun8i-h3-r-intc

              - allwinner,sun50i-a64-r-intc

          - const: allwinner,sun6i-a31-r-intc

      - const: allwinner,sun50i-h6-r-intc



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1

    description:

      The GIC interrupt labeled as "External NMI".



  interrupt-controller: true



required:

  - "#interrupt-cells"

  - compatible

  - reg

  - interrupts

  - interrupt-controller



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    r_intc: interrupt-controller@1f00c00 {

            compatible = "allwinner,sun50i-a64-r-intc",

                         "allwinner,sun6i-a31-r-intc";

            interrupt-controller;

            #interrupt-cells = <3>;

            reg = <0x01f00c00 0x400>;

            interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

    };



...

Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml

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@@ -22,23 +22,13 @@ properties: 


  compatible:

    oneOf:

      - const: allwinner,sun6i-a31-r-intc

      - const: allwinner,sun6i-a31-sc-nmi

        deprecated: true

      - const: allwinner,sun7i-a20-sc-nmi

      - items:

          - const: allwinner,sun8i-a83t-r-intc

          - const: allwinner,sun6i-a31-r-intc

      - const: allwinner,sun9i-a80-nmi

      - items:

          - const: allwinner,sun50i-a64-r-intc

          - const: allwinner,sun6i-a31-r-intc

      - items:

          - const: allwinner,sun50i-a100-nmi

          - const: allwinner,sun9i-a80-nmi

      - items:

          - const: allwinner,sun50i-h6-r-intc

          - const: allwinner,sun6i-a31-r-intc



  reg:

    maxItems: 1

Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt

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@@ -20,6 +20,8 @@ Properties: 
	Definition: Should contain "qcom,<soc>-pdc" and "qcom,pdc"

		    - "qcom,sc7180-pdc": For SC7180

		    - "qcom,sdm845-pdc": For SDM845

		    - "qcom,sdm8250-pdc": For SM8250

		    - "qcom,sdm8350-pdc": For SM8350



- reg:

	Usage: required

Documentation/devicetree/bindings/interrupt-controller/realtek,rtl-intc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/interrupt-controller/realtek,rtl-intc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Realtek RTL SoC interrupt controller devicetree bindings



maintainers:

  - Birger Koblitz <mail@birger-koblitz.de>

  - Bert Vermeulen <bert@biot.com>

  - John Crispin <john@phrozen.org>



properties:

  compatible:

    const: realtek,rtl-intc



  "#interrupt-cells":

    const: 1



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  interrupt-controller: true



  "#address-cells":

    const: 0



  interrupt-map:

    description: Describes mapping from SoC interrupts to CPU interrupts



required:

  - compatible

  - reg

  - "#interrupt-cells"

  - interrupt-controller

  - "#address-cells"

  - interrupt-map



additionalProperties: false



examples:

  - |

    intc: interrupt-controller@3000 {

      compatible = "realtek,rtl-intc";

      #interrupt-cells = <1>;

      interrupt-controller;

      reg = <0x3000 0x20>;

      #address-cells = <0>;

      interrupt-map =

              <31 &cpuintc 2>,

              <30 &cpuintc 1>,

              <29 &cpuintc 5>;

    };

Documentation/devicetree/bindings/interrupt-controller/sigma,smp8642-intc.txt

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Sigma Designs SMP86xx/SMP87xx secondary interrupt controller



Required properties:

- compatible: should be "sigma,smp8642-intc"

- reg: physical address of MMIO region

- ranges: address space mapping of child nodes

- interrupt-controller: boolean

- #address-cells: should be <1>

- #size-cells: should be <1>



One child node per control block with properties:

- reg: address of registers for this control block

- interrupt-controller: boolean

- #interrupt-cells: should be <2>, interrupt index and flags per interrupts.txt

- interrupts: interrupt spec of primary interrupt controller



Example:



interrupt-controller@6e000 {

	compatible = "sigma,smp8642-intc";

	reg = <0x6e000 0x400>;

	ranges = <0x0 0x6e000 0x400>;

	interrupt-parent = <&gic>;

	interrupt-controller;

	#address-cells = <1>;

	#size-cells = <1>;



	irq0: interrupt-controller@0 {

		reg = <0x000 0x100>;

		interrupt-controller;

		#interrupt-cells = <2>;

		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;

	};



	irq1: interrupt-controller@100 {

		reg = <0x100 0x100>;

		interrupt-controller;

		#interrupt-cells = <2>;

		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;

	};



	irq2: interrupt-controller@300 {

		reg = <0x300 0x100>;

		interrupt-controller;

		#interrupt-cells = <2>;

		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;

	};

};