Commit 0b51c08b authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'remotes/lorenzo/pci/mediatek' 

- Configure FC and FTS for functions other than 0 (Ryder Lee)

- Add missing MODULE_DEVICE_TABLE (Qiheng Lin)

- Add YAML schema for MediaTek (Jianjun Wang)

- Export pci_pio_to_address() for module use (Jianjun Wang)

- Add MediaTek MT8192 PCIe controller driver (Jianjun Wang)

- Add MediaTek MT8192 INTx support (Jianjun Wang)

- Add MediaTek MT8192 MSI support (Jianjun Wang)

- Add MediaTek MT8192 system power management support (Jianjun Wang)

* remotes/lorenzo/pci/mediatek:
  MAINTAINERS: Add Jianjun Wang as MediaTek PCI co-maintainer
  PCI: mediatek-gen3: Add system PM support
  PCI: mediatek-gen3: Add MSI support
  PCI: mediatek-gen3: Add INTx support
  PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192
  PCI: Export pci_pio_to_address() for module use
  dt-bindings: PCI: mediatek-gen3: Add YAML schema
  PCI: mediatek: Add missing MODULE_DEVICE_TABLE
  PCI: mediatek: Configure FC and FTS for functions other than 0
parents 586fbe90 0739191b

Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Gen3 PCIe controller on MediaTek SoCs



maintainers:

  - Jianjun Wang <jianjun.wang@mediatek.com>



description: |+

  PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed

  and compatible with Gen2, Gen1 speed.



  This PCIe controller supports up to 256 MSI vectors, the MSI hardware

  block diagram is as follows:



                    +-----+

                    | GIC |

                    +-----+

                       ^

                       |

                   port->irq

                       |

               +-+-+-+-+-+-+-+-+

               |0|1|2|3|4|5|6|7| (PCIe intc)

               +-+-+-+-+-+-+-+-+

                ^ ^           ^

                | |    ...    |

        +-------+ +------+    +-----------+

        |                |                |

  +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+

  |0|1|...|30|31|  |0|1|...|30|31|  |0|1|...|30|31| (MSI sets)

  +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+

   ^ ^      ^  ^    ^ ^      ^  ^    ^ ^      ^  ^

   | |      |  |    | |      |  |    | |      |  |  (MSI vectors)

   | |      |  |    | |      |  |    | |      |  |



    (MSI SET0)       (MSI SET1)  ...   (MSI SET7)



  With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,

  each set has its own address for MSI message, and supports 32 MSI vectors

  to generate interrupt.



allOf:

  - $ref: /schemas/pci/pci-bus.yaml#



properties:

  compatible:

    const: mediatek,mt8192-pcie



  reg:

    maxItems: 1



  reg-names:

    items:

      - const: pcie-mac



  interrupts:

    maxItems: 1



  ranges:

    minItems: 1

    maxItems: 8



  resets:

    minItems: 1

    maxItems: 2



  reset-names:

    minItems: 1

    maxItems: 2

    items:

      - const: phy

      - const: mac



  clocks:

    maxItems: 6



  clock-names:

    items:

      - const: pl_250m

      - const: tl_26m

      - const: tl_96m

      - const: tl_32k

      - const: peri_26m

      - const: top_133m



  assigned-clocks:

    maxItems: 1



  assigned-clock-parents:

    maxItems: 1



  phys:

    maxItems: 1



  '#interrupt-cells':

    const: 1



  interrupt-controller:

    description: Interrupt controller node for handling legacy PCI interrupts.

    type: object

    properties:

      '#address-cells':

        const: 0

      '#interrupt-cells':

        const: 1

      interrupt-controller: true



    required:

      - '#address-cells'

      - '#interrupt-cells'

      - interrupt-controller



    additionalProperties: false



required:

  - compatible

  - reg

  - reg-names

  - interrupts

  - ranges

  - clocks

  - '#interrupt-cells'

  - interrupt-controller



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interrupt-controller/irq.h>



    bus {

        #address-cells = <2>;

        #size-cells = <2>;



        pcie: pcie@11230000 {

            compatible = "mediatek,mt8192-pcie";

            device_type = "pci";

            #address-cells = <3>;

            #size-cells = <2>;

            reg = <0x00 0x11230000 0x00 0x4000>;

            reg-names = "pcie-mac";

            interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;

            bus-range = <0x00 0xff>;

            ranges = <0x82000000 0x00 0x12000000 0x00

                      0x12000000 0x00 0x1000000>;

            clocks = <&infracfg 44>,

                     <&infracfg 40>,

                     <&infracfg 43>,

                     <&infracfg 97>,

                     <&infracfg 99>,

                     <&infracfg 111>;

            clock-names = "pl_250m", "tl_26m", "tl_96m",

                          "tl_32k", "peri_26m", "top_133m";

            assigned-clocks = <&topckgen 50>;

            assigned-clock-parents = <&topckgen 91>;



            phys = <&pciephy>;

            phy-names = "pcie-phy";



            resets = <&infracfg_rst 2>,

                     <&infracfg_rst 3>;

            reset-names = "phy", "mac";



            #interrupt-cells = <1>;

            interrupt-map-mask = <0 0 0 0x7>;

            interrupt-map = <0 0 0 1 &pcie_intc 0>,

                            <0 0 0 2 &pcie_intc 1>,

                            <0 0 0 3 &pcie_intc 2>,

                            <0 0 0 4 &pcie_intc 3>;

            pcie_intc: interrupt-controller {

                      #address-cells = <0>;

                      #interrupt-cells = <1>;

                      interrupt-controller;

            };

        };

    };

MAINTAINERS

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@@ -13919,6 +13919,7 @@ F: drivers/pci/controller/dwc/pcie-histb.c 








PCIE DRIVER FOR MEDIATEK









M:	Ryder Lee <ryder.lee@mediatek.com>









M:	Jianjun Wang <jianjun.wang@mediatek.com>









L:	linux-pci@vger.kernel.org









L:	linux-mediatek@lists.infradead.org









S:	Supported
































drivers/pci/controller/Kconfig



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@@ -233,6 +233,19 @@ config PCIE_MEDIATEK







	  Say Y here if you want to enable PCIe controller support on









	  MediaTek SoCs.



















config PCIE_MEDIATEK_GEN3









	tristate "MediaTek Gen3 PCIe controller"









	depends on ARCH_MEDIATEK || COMPILE_TEST









	depends on PCI_MSI_IRQ_DOMAIN









	help









	  Adds support for PCIe Gen3 MAC controller for MediaTek SoCs.









	  This PCIe controller is compatible with Gen3, Gen2 and Gen1 speed,









	  and support up to 256 MSI interrupt numbers for









	  multi-function devices.



















	  Say Y here if you want to enable Gen3 PCIe controller support on









	  MediaTek SoCs.



















config VMD









	depends on PCI_MSI && X86_64 && SRCU









	tristate "Intel Volume Management Device Driver"
































drivers/pci/controller/Makefile



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@@ -30,6 +30,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o







obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o









obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o









obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o









obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie-mediatek-gen3.o









obj-$(CONFIG_PCIE_MICROCHIP_HOST) += pcie-microchip-host.o









obj-$(CONFIG_VMD) += vmd.o









obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
































drivers/pci/controller/pcie-mediatek-gen3.c
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