dt-bindings: memory: convert Samsung Exynos DMC to dtschema

* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device

The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM

memory chips are connected. The driver is to monitor the controller in runtime

and switch frequency and voltage. To monitor the usage of the controller in

runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which

is able to measure the current load of the memory.

When 'userspace' governor is used for the driver, an application is able to

switch the DMC and memory frequency.

Required properties for DMC device for Exynos5422:

- compatible: Should be "samsung,exynos5422-dmc".

- clocks : list of clock specifiers, must contain an entry for each

  required entry in clock-names for CLK_FOUT_SPLL, CLK_MOUT_SCLK_SPLL,

  CLK_FF_DOUT_SPLL2, CLK_FOUT_BPLL, CLK_MOUT_BPLL, CLK_SCLK_BPLL,

  CLK_MOUT_MX_MSPLL_CCORE, CLK_MOUT_MX_MSPLL_CCORE_PHY, CLK_MOUT_MCLK_CDREX,

- clock-names : should include "fout_spll", "mout_sclk_spll", "ff_dout_spll2",

  "fout_bpll", "mout_bpll", "sclk_bpll", "mout_mx_mspll_ccore",

  "mout_mclk_cdrex"  entries

- devfreq-events : phandles for PPMU devices connected to this DMC.

- vdd-supply : phandle for voltage regulator which is connected.

- reg : registers of two CDREX controllers.

- operating-points-v2 : phandle for OPPs described in v2 definition.

- device-handle : phandle of the connected DRAM memory device. For more

	information please refer to documentation file:

	Documentation/devicetree/bindings/ddr/lpddr3.txt

- devfreq-events : phandles of the PPMU events used by the controller.

- samsung,syscon-clk : phandle of the clock register set used by the controller,

	these registers are used for enabling a 'pause' feature and are not

	exposed by clock framework but they must be used in a safe way.

	The register offsets are in the driver code and specyfic for this SoC

	type.

Optional properties for DMC device for Exynos5422:

- interrupt-parent : The parent interrupt controller.

- interrupts : Contains the IRQ line numbers for the DMC internal performance

  event counters in DREX0 and DREX1 channels. Align with specification of the

  interrupt line(s) in the interrupt-parent controller.

- interrupt-names : IRQ names "drex_0" and "drex_1", the order should be the

  same as in the 'interrupts' list above.

Example:

	ppmu_dmc0_0: ppmu@10d00000 {

		compatible = "samsung,exynos-ppmu";

		reg = <0x10d00000 0x2000>;

		clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;

		clock-names = "ppmu";

		events {

			ppmu_event_dmc0_0: ppmu-event3-dmc0_0 {

				event-name = "ppmu-event3-dmc0_0";

			};

		};

	};

	dmc: memory-controller@10c20000 {

		compatible = "samsung,exynos5422-dmc";

		reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;

		clocks = <&clock CLK_FOUT_SPLL>,

			 <&clock CLK_MOUT_SCLK_SPLL>,

			 <&clock CLK_FF_DOUT_SPLL2>,

			 <&clock CLK_FOUT_BPLL>,

			 <&clock CLK_MOUT_BPLL>,

			 <&clock CLK_SCLK_BPLL>,

			 <&clock CLK_MOUT_MX_MSPLL_CCORE>,

			 <&clock CLK_MOUT_MCLK_CDREX>;

		clock-names = "fout_spll",

			      "mout_sclk_spll",

			      "ff_dout_spll2",

			      "fout_bpll",

			      "mout_bpll",

			      "sclk_bpll",

			      "mout_mx_mspll_ccore",

			      "mout_mclk_cdrex";

		operating-points-v2 = <&dmc_opp_table>;

		devfreq-events = <&ppmu_event3_dmc0_0>,	<&ppmu_event3_dmc0_1>,

				 <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;

		device-handle = <&samsung_K3QF2F20DB>;

		vdd-supply = <&buck1_reg>;

		samsung,syscon-clk = <&clock>;

		interrupt-parent = <&combiner>;

		interrupts = <16 0>, <16 1>;

		interrupt-names = "drex_0", "drex_1";

	};

# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/memory-controllers/samsung,exynos5422-dmc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: |

  Samsung Exynos5422 SoC frequency and voltage scaling for Dynamic Memory

  Controller device

maintainers:

  - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>

  - Lukasz Luba <lukasz.luba@arm.com>

description: |

  The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the

  DRAM memory chips are connected. The driver is to monitor the controller in

  runtime and switch frequency and voltage. To monitor the usage of the

  controller in runtime, the driver uses the PPMU (Platform Performance

  Monitoring Unit), which is able to measure the current load of the memory.

  When 'userspace' governor is used for the driver, an application is able to

  switch the DMC and memory frequency.

properties:

  compatible:

    items:

      - const: samsung,exynos5422-dmc

  clock-names:

    items:

      - const: fout_spll

      - const: mout_sclk_spll

      - const: ff_dout_spll2

      - const: fout_bpll

      - const: mout_bpll

      - const: sclk_bpll

      - const: mout_mx_mspll_ccore

      - const: mout_mclk_cdrex

  clocks:

    minItems: 8

    maxItems: 8

  devfreq-events:

    $ref: '/schemas/types.yaml#/definitions/phandle-array'

    minItems: 1

    maxItems: 16

    description: phandles of the PPMU events used by the controller.

  device-handle:

    $ref: '/schemas/types.yaml#/definitions/phandle'

    description: |

      phandle of the connected DRAM memory device. For more information please

      refer to documentation file: Documentation/devicetree/bindings/ddr/lpddr3.txt

  operating-points-v2: true

  interrupts:

    items:

      - description: DMC internal performance event counters in DREX0

      - description: DMC internal performance event counters in DREX1

  interrupt-names:

    items:

      - const: drex_0

      - const: drex_1

  reg:

    items:

      - description: registers of DREX0

      - description: registers of DREX1

  samsung,syscon-clk:

    $ref: '/schemas/types.yaml#/definitions/phandle'

    description: |

      Phandle of the clock register set used by the controller, these registers

      are used for enabling a 'pause' feature and are not exposed by clock

      framework but they must be used in a safe way.  The register offsets are

      in the driver code and specyfic for this SoC type.

  vdd-supply: true

required:

  - compatible

  - clock-names

  - clocks

  - devfreq-events

  - device-handle

  - reg

  - samsung,syscon-clk

additionalProperties: false

examples:

  - |

    #include <dt-bindings/clock/exynos5420.h>

    ppmu_dmc0_0: ppmu@10d00000 {

        compatible = "samsung,exynos-ppmu";

        reg = <0x10d00000 0x2000>;

        clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;

        clock-names = "ppmu";

        events {

            ppmu_event_dmc0_0: ppmu-event3-dmc0-0 {

                event-name = "ppmu-event3-dmc0_0";

            };

        };

    };

    memory-controller@10c20000 {

        compatible = "samsung,exynos5422-dmc";

        reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;

        clocks = <&clock CLK_FOUT_SPLL>,

                 <&clock CLK_MOUT_SCLK_SPLL>,

                 <&clock CLK_FF_DOUT_SPLL2>,

                 <&clock CLK_FOUT_BPLL>,

                 <&clock CLK_MOUT_BPLL>,

                 <&clock CLK_SCLK_BPLL>,

                 <&clock CLK_MOUT_MX_MSPLL_CCORE>,

                 <&clock CLK_MOUT_MCLK_CDREX>;

        clock-names = "fout_spll",

                      "mout_sclk_spll",

                      "ff_dout_spll2",

                      "fout_bpll",

                      "mout_bpll",

                      "sclk_bpll",

                      "mout_mx_mspll_ccore",

                      "mout_mclk_cdrex";

        operating-points-v2 = <&dmc_opp_table>;

        devfreq-events = <&ppmu_event3_dmc0_0>,	<&ppmu_event3_dmc0_1>,

                         <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;

        device-handle = <&samsung_K3QF2F20DB>;

        vdd-supply = <&buck1_reg>;

        samsung,syscon-clk = <&clock>;

        interrupt-parent = <&combiner>;

        interrupts = <16 0>, <16 1>;

        interrupt-names = "drex_0", "drex_1";

    };

L:	linux-pm@vger.kernel.org

L:	linux-samsung-soc@vger.kernel.org

S:	Maintained

F:	Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt

F:	Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml

F:	drivers/memory/samsung/exynos5422-dmc.c

DME1737 HARDWARE MONITOR DRIVER