Unverified Commit 0b308045 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!4637 Using smmu IIDR registers 

Merge Pull Request from: @ci-robot 
 
PR sync from: Zhang Zekun <zhangzekun11@huawei.com>
https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/TZEO6K4HGKPCHZONETZPZH63JHNNW5MH/ 
Using the smmu registers to identify the problem described
in commit 8544c8e1 ("iommu/arm-smmu-v3: Add a SYNC command
to avoid broken page table prefetch")

Zhang Zekun (2):
  Revert "iommu/arm-smmu-v3: Add a SYNC command to avoid broken page
    table prefetch"
  iommu/arm-smmu-v3: Enable iotlb_sync_map according to SMMU_IIDR


-- 
2.17.1
 
https://gitee.com/src-openeuler/kernel/issues/I92MAE 
 
Link:https://gitee.com/openeuler/kernel/pulls/4637

 

Reviewed-by: default avatarWeilong Chen <chenweilong@huawei.com>
Reviewed-by: default avatarLiu Chao <liuchao173@huawei.com>
Reviewed-by: default avatarZhang Jianhua <chris.zjh@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parents 29eb4be7 0b84ef37

Documentation/arch/arm64/silicon-errata.rst

+1 −0
Original line number Diff line number Diff line
@@ -207,6 +207,7 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| Hisilicon      | LINXICORE9100   | #1980005        | HISILICON_ERRATUM_1980005   |

+----------------+-----------------+-----------------+-----------------------------+

| Hisilicon      | SMMUv3          | #162100602      | HISILICON_ERRATUM_162100602 |

+----------------+-----------------+-----------------+-----------------------------+

| Qualcomm Tech. | Kryo/Falkor v1  | E1003           | QCOM_FALKOR_ERRATUM_1003    |

+----------------+-----------------+-----------------+-----------------------------+

arch/arm64/Kconfig

+5 −6
Original line number Diff line number Diff line
@@ -1187,14 +1187,13 @@ config HISILICON_ERRATUM_1980005 


config HISILICON_ERRATUM_162100602

	bool "Hisilicon erratum 162100602"

	depends on ARM_SMMU_V3

	depends on ARM_SMMU_V3 && ARCH_HISI

	default y

	help

	  On Hisilicon LINXICORE9100 cores, SMMU pagetable prefetch features may

	  prefetch and use a invalid PTE even the PTE is valid at that time. This

	  will cause the device trigger fake pagefaults. If the SMMU works in

	  terminate mode, transactions which occur fake pagefaults will be aborted,

	  and could result in unexpected errors.

	  SMMU pagetable prefetch features may prefetch and use a invalid PTE even

	  the PTE is valid at that time. This will cause the device trigger fake

	  pagefaults. If the SMMU works in terminate mode, transactions which occur

	  fake pagefaults will be aborted, and could result in unexpected errors.



	  If unsure, say Y.

arch/arm64/kernel/cpu_errata.c

+0 −14
Original line number Diff line number Diff line
@@ -360,13 +360,6 @@ static const struct midr_range hisilicon_erratum_162100125_cpus[] = { 
};

#endif



#ifdef CONFIG_HISILICON_ERRATUM_162100602

static const struct midr_range hisilicon_erratum_162100602_cpus[] = {

	MIDR_REV(MIDR_HISI_LINXICORE9100, 0, 0),

	{},

};

#endif



#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003

static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = {

	{
@@ -598,13 +591,6 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		ERRATA_MIDR_RANGE_LIST(hisilicon_erratum_162100125_cpus),

	},

#endif

#ifdef CONFIG_HISILICON_ERRATUM_162100602

	{

		.desc = "Hisilicon erratum 162100602",

		.capability = ARM64_WORKAROUND_HISILICON_ERRATUM_162100602,

		ERRATA_MIDR_RANGE_LIST(hisilicon_erratum_162100602_cpus),

	},

#endif

#ifdef CONFIG_HISILICON_ERRATUM_1980005

	{

		.desc = "Hisilicon erratum 1980005 (IDC)",

arch/arm64/tools/cpucaps

+0 −1
Original line number Diff line number Diff line
@@ -105,7 +105,6 @@ WORKAROUND_SPECULATIVE_AT 
WORKAROUND_HISILICON_ERRATUM_162100125

WORKAROUND_HISI_HIP08_RU_PREFETCH

WORKAROUND_HISILICON_1980005

WORKAROUND_HISILICON_ERRATUM_162100602

KABI_RESERVE_1

KABI_RESERVE_2

KABI_RESERVE_3

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

+10 −3
Original line number Diff line number Diff line
@@ -2783,7 +2783,7 @@ static void arm_smmu_iotlb_sync_map(struct iommu_domain *domain, 
	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);

	size_t granule_size;



	if (!cpus_have_const_cap(ARM64_WORKAROUND_HISILICON_ERRATUM_162100602))

	if (!(smmu_domain->smmu->options & ARM_SMMU_OPT_SYNC_MAP))

		return;



	granule_size = 1 <<  __ffs(smmu_domain->domain.pgsize_bitmap);
@@ -4247,6 +4247,13 @@ static void arm_smmu_device_iidr_probe(struct arm_smmu_device *smmu) 
		}

		break;

	}



#ifdef CONFIG_HISILICON_ERRATUM_162100602

	reg = readl_relaxed(smmu->base + ARM_SMMU_IIDR);

	if (FIELD_GET(IIDR_VARIANT, reg) == 0x3 &&

	    FIELD_GET(IIDR_REVISION, reg) == 0x2)

		smmu->options |= ARM_SMMU_OPT_SYNC_MAP;

#endif

}



static void arm_smmu_get_httu(struct arm_smmu_device *smmu, u32 reg)