Commit 0b15b1ec authored by Duncan Ma's avatar Duncan Ma Committed by Alex Deucher
Browse files

drm/amd/display: Correct dram channel width for dcn314 



[Why]
The interpretation of the number of memory channels
differ by memory type, and this affects channel width
for the DML input.

[How]
Set dram channel width according to memory type for
dcn314.

Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: default avatarNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarPavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: default avatarDuncan Ma <duncan.ma@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 82c40184

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

+2 −0
Original line number Diff line number Diff line
@@ -670,6 +670,8 @@ static void dcn314_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *cl 
	}

	ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz);

	bw_params->vram_type = bios_info->memory_type;



	bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4;

	bw_params->num_channels = bios_info->ma_channel_number ? bios_info->ma_channel_number : 4;



	for (i = 0; i < WM_SET_COUNT; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

+3 −0
Original line number Diff line number Diff line
@@ -194,6 +194,9 @@ void dcn314_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_p 
		dcn3_14_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;

		dcn3_14_ip.max_num_dpp = dc->res_pool->pipe_count;



		if (bw_params->dram_channel_width_bytes > 0)

			dcn3_14_soc.dram_channel_width_bytes = bw_params->dram_channel_width_bytes;



		if (bw_params->num_channels > 0)

			dcn3_14_soc.num_chans = bw_params->num_channels;

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

+1 −0
Original line number Diff line number Diff line
@@ -214,6 +214,7 @@ struct dummy_pstate_entry { 
struct clk_bw_params {

	unsigned int vram_type;

	unsigned int num_channels;

	unsigned int dram_channel_width_bytes;

 	unsigned int dispclk_vco_khz;

	unsigned int dc_mode_softmax_memclk;

	struct clk_limit_table clk_table;