Commit 0b086d76 authored Mar 10, 2023 by Arınç ÜNAL Committed by Jakub Kicinski Mar 13, 2023

net: dsa: mt7530: set PLL frequency and trgmii only when trgmii is used

As my testing on the MCM MT7530 switch on MT7621 SoC shows, setting the PLL
frequency does not affect MII modes other than trgmii on port 5 and port 6.
So the assumption is that the operation here called "setting the PLL
frequency" actually sets the frequency of the TRGMII TX clock.

Make it so that it and the rest of the trgmii setup run only when the
trgmii mode is used.

Tested rgmii and trgmii modes of port 6 on MCM MT7530 on MT7621AT Unielec
U7621-06 and standalone MT7530 on MT7623NI Bananapi BPI-R2.

Fixes: b8f126a8 ("net-next: dsa: add dsa support for Mediatek MT7530 switch")
Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Link: https://lore.kernel.org/r/20230310073338.5836-2-arinc.unal@arinc9.com

Signed-off-by: Jakub Kicinski <kuba@kernel.org>

parent feb03fd1

drivers/net/dsa/mt7530.c

+31 −31

Original line number	Diff line number	Diff line
		@@ -430,8 +430,6 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
		switch (interface) {
		case PHY_INTERFACE_MODE_RGMII:
		trgint = 0;
		/* PLL frequency: 125MHz */
		ncpo1 = 0x0c80;
		break;
		case PHY_INTERFACE_MODE_TRGMII:
		trgint = 1;
		@@ -462,6 +460,7 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
		mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
		P6_INTF_MODE(trgint));

		if (trgint) {
		/* Lower Tx Driving for TRGMII path */
		for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
		mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
		@@ -489,11 +488,12 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
		/* Enable MT7530 core and TRGMII Tx clocks */
		core_set(priv, CORE_TRGMII_GSW_CLK_CG,
		REG_GSWCK_EN \| REG_TRGMIICK_EN);

		if (!trgint)
		} else {
		for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
		mt7530_rmw(priv, MT7530_TRGMII_RD(i),
		RD_TAP_MASK, RD_TAP(16));
		}

		return 0;
		}