Commit 0b023410 authored by Darren Powell's avatar Darren Powell Committed by Alex Deucher
Browse files

amdgpu/pm: Replace vega12,20 usage of sprintf with sysfs_emit 



=== Test ===
AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1`
AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | awk '{print $9}'`
HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON}
LOGFILE=pp_printf.test.log

lspci -nn | grep "VGA\|Display"  > $LOGFILE
FILES="pp_dpm_sclk
pp_features
pp_power_profile_mode "

for f in $FILES
do
  echo === $f === >> $LOGFILE
  cat $HWMON_DIR/device/$f >> $LOGFILE
done
cat $LOGFILE

Signed-off-by: default avatarDarren Powell <darren.powell@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 21f0742a

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

+7 −7
Original line number Diff line number Diff line
@@ -2146,13 +2146,13 @@ static int vega12_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf) 
		"[EnableAllSmuFeatures] Failed to get enabled smc features!",

		return ret);



	size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);

	size += sprintf(buf + size, "%-19s %-22s %s\n",

	size += sysfs_emit_at(buf, size, "Current ppfeatures: 0x%016llx\n", features_enabled);

	size += sysfs_emit_at(buf, size, "%-19s %-22s %s\n",

				output_title[0],

				output_title[1],

				output_title[2]);

	for (i = 0; i < GNLD_FEATURES_MAX; i++) {

		size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",

		size += sysfs_emit_at(buf, size, "%-19s 0x%016llx %6s\n",

				ppfeature_name[i],

				1ULL << i,

				(features_enabled & (1ULL << i)) ? "Y" : "N");
@@ -2256,7 +2256,7 @@ static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr, 
				"Attempt to get gfx clk levels Failed!",

				return -1);

		for (i = 0; i < clocks.num_levels; i++)

			size += sprintf(buf + size, "%d: %uMhz %s\n",

			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",

				i, clocks.data[i].clocks_in_khz / 1000,

				(clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : "");

		break;
@@ -2272,7 +2272,7 @@ static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr, 
				"Attempt to get memory clk levels Failed!",

				return -1);

		for (i = 0; i < clocks.num_levels; i++)

			size += sprintf(buf + size, "%d: %uMhz %s\n",

			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",

				i, clocks.data[i].clocks_in_khz / 1000,

				(clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : "");

		break;
@@ -2290,7 +2290,7 @@ static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr, 
				"Attempt to get soc clk levels Failed!",

				return -1);

		for (i = 0; i < clocks.num_levels; i++)

			size += sprintf(buf + size, "%d: %uMhz %s\n",

			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",

				i, clocks.data[i].clocks_in_khz / 1000,

				(clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : "");

		break;
@@ -2308,7 +2308,7 @@ static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr, 
				"Attempt to get dcef clk levels Failed!",

				return -1);

		for (i = 0; i < clocks.num_levels; i++)

			size += sprintf(buf + size, "%d: %uMhz %s\n",

			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",

				i, clocks.data[i].clocks_in_khz / 1000,

				(clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : "");

		break;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

+37 −37
Original line number Diff line number Diff line
@@ -3243,13 +3243,13 @@ static int vega20_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf) 
			"[EnableAllSmuFeatures] Failed to get enabled smc features!",

			return ret);



	size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);

	size += sprintf(buf + size, "%-19s %-22s %s\n",

	size += sysfs_emit_at(buf, size, "Current ppfeatures: 0x%016llx\n", features_enabled);

	size += sysfs_emit_at(buf, size, "%-19s %-22s %s\n",

				output_title[0],

				output_title[1],

				output_title[2]);

	for (i = 0; i < GNLD_FEATURES_MAX; i++) {

		size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",

		size += sysfs_emit_at(buf, size, "%-19s 0x%016llx %6s\n",

					ppfeature_name[i],

					1ULL << i,

					(features_enabled & (1ULL << i)) ? "Y" : "N");
@@ -3372,13 +3372,13 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr, 
				return ret);



		if (vega20_get_sclks(hwmgr, &clocks)) {

			size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",

			size += sysfs_emit_at(buf, size, "0: %uMhz * (DPM disabled)\n",

				now / 100);

			break;

		}



		for (i = 0; i < clocks.num_levels; i++)

			size += sprintf(buf + size, "%d: %uMhz %s\n",

			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",

				i, clocks.data[i].clocks_in_khz / 1000,

				(clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");

		break;
@@ -3390,13 +3390,13 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr, 
				return ret);



		if (vega20_get_memclocks(hwmgr, &clocks)) {

			size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",

			size += sysfs_emit_at(buf, size, "0: %uMhz * (DPM disabled)\n",

				now / 100);

			break;

		}



		for (i = 0; i < clocks.num_levels; i++)

			size += sprintf(buf + size, "%d: %uMhz %s\n",

			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",

				i, clocks.data[i].clocks_in_khz / 1000,

				(clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");

		break;
@@ -3408,13 +3408,13 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr, 
				return ret);



		if (vega20_get_socclocks(hwmgr, &clocks)) {

			size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",

			size += sysfs_emit_at(buf, size, "0: %uMhz * (DPM disabled)\n",

				now / 100);

			break;

		}



		for (i = 0; i < clocks.num_levels; i++)

			size += sprintf(buf + size, "%d: %uMhz %s\n",

			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",

				i, clocks.data[i].clocks_in_khz / 1000,

				(clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");

		break;
@@ -3426,7 +3426,7 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr, 
				return ret);



		for (i = 0; i < fclk_dpm_table->count; i++)

			size += sprintf(buf + size, "%d: %uMhz %s\n",

			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",

				i, fclk_dpm_table->dpm_levels[i].value,

				fclk_dpm_table->dpm_levels[i].value == (now / 100) ? "*" : "");

		break;
@@ -3438,13 +3438,13 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr, 
				return ret);



		if (vega20_get_dcefclocks(hwmgr, &clocks)) {

			size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",

			size += sysfs_emit_at(buf, size, "0: %uMhz * (DPM disabled)\n",

				now / 100);

			break;

		}



		for (i = 0; i < clocks.num_levels; i++)

			size += sprintf(buf + size, "%d: %uMhz %s\n",

			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",

				i, clocks.data[i].clocks_in_khz / 1000,

				(clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");

		break;
@@ -3458,7 +3458,7 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr, 
			gen_speed = pptable->PcieGenSpeed[i];

			lane_width = pptable->PcieLaneCount[i];



			size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,

			size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,

					(gen_speed == 0) ? "2.5GT/s," :

					(gen_speed == 1) ? "5.0GT/s," :

					(gen_speed == 2) ? "8.0GT/s," :
@@ -3479,18 +3479,18 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr, 
	case OD_SCLK:

		if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&

		    od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {

			size = sprintf(buf, "%s:\n", "OD_SCLK");

			size += sprintf(buf + size, "0: %10uMhz\n",

			size = sysfs_emit(buf, "%s:\n", "OD_SCLK");

			size += sysfs_emit_at(buf, size, "0: %10uMhz\n",

				od_table->GfxclkFmin);

			size += sprintf(buf + size, "1: %10uMhz\n",

			size += sysfs_emit_at(buf, size, "1: %10uMhz\n",

				od_table->GfxclkFmax);

		}

		break;



	case OD_MCLK:

		if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {

			size = sprintf(buf, "%s:\n", "OD_MCLK");

			size += sprintf(buf + size, "1: %10uMhz\n",

			size = sysfs_emit(buf, "%s:\n", "OD_MCLK");

			size += sysfs_emit_at(buf, size, "1: %10uMhz\n",

				od_table->UclkFmax);

		}
@@ -3503,14 +3503,14 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr, 
		    od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&

		    od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&

		    od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {

			size = sprintf(buf, "%s:\n", "OD_VDDC_CURVE");

			size += sprintf(buf + size, "0: %10uMhz %10dmV\n",

			size = sysfs_emit(buf, "%s:\n", "OD_VDDC_CURVE");

			size += sysfs_emit_at(buf, size, "0: %10uMhz %10dmV\n",

				od_table->GfxclkFreq1,

				od_table->GfxclkVolt1 / VOLTAGE_SCALE);

			size += sprintf(buf + size, "1: %10uMhz %10dmV\n",

			size += sysfs_emit_at(buf, size, "1: %10uMhz %10dmV\n",

				od_table->GfxclkFreq2,

				od_table->GfxclkVolt2 / VOLTAGE_SCALE);

			size += sprintf(buf + size, "2: %10uMhz %10dmV\n",

			size += sysfs_emit_at(buf, size, "2: %10uMhz %10dmV\n",

				od_table->GfxclkFreq3,

				od_table->GfxclkVolt3 / VOLTAGE_SCALE);

		}
@@ -3518,17 +3518,17 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr, 
		break;



	case OD_RANGE:

		size = sprintf(buf, "%s:\n", "OD_RANGE");

		size = sysfs_emit(buf, "%s:\n", "OD_RANGE");



		if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&

		    od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {

			size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",

			size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",

				od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,

				od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);

		}



		if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {

			size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",

			size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",

				od8_settings[OD8_SETTING_UCLK_FMAX].min_value,

				od8_settings[OD8_SETTING_UCLK_FMAX].max_value);

		}
@@ -3539,22 +3539,22 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr, 
		    od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&

		    od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&

		    od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {

			size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",

			size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",

				od8_settings[OD8_SETTING_GFXCLK_FREQ1].min_value,

				od8_settings[OD8_SETTING_GFXCLK_FREQ1].max_value);

			size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",

			size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",

				od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].min_value,

				od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].max_value);

			size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",

			size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",

				od8_settings[OD8_SETTING_GFXCLK_FREQ2].min_value,

				od8_settings[OD8_SETTING_GFXCLK_FREQ2].max_value);

			size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",

			size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",

				od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].min_value,

				od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].max_value);

			size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",

			size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",

				od8_settings[OD8_SETTING_GFXCLK_FREQ3].min_value,

				od8_settings[OD8_SETTING_GFXCLK_FREQ3].max_value);

			size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",

			size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",

				od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].min_value,

				od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].max_value);

		}
@@ -4003,7 +4003,7 @@ static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) 
	if (!buf)

		return -EINVAL;



	size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",

	size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",

			title[0], title[1], title[2], title[3], title[4], title[5],

			title[6], title[7], title[8], title[9], title[10]);
@@ -4016,10 +4016,10 @@ static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) 
				"[GetPowerProfile] Failed to get activity monitor!",

				return result);



		size += sprintf(buf + size, "%2d %14s%s:\n",

		size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",

			i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ");



		size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",

		size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",

			" ",

			0,

			"GFXCLK",
@@ -4033,7 +4033,7 @@ static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) 
			activity_monitor.Gfx_PD_Data_error_coeff,

			activity_monitor.Gfx_PD_Data_error_rate_coeff);



		size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",

		size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",

			" ",

			1,

			"SOCCLK",
@@ -4047,7 +4047,7 @@ static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) 
			activity_monitor.Soc_PD_Data_error_coeff,

			activity_monitor.Soc_PD_Data_error_rate_coeff);



		size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",

		size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",

			" ",

			2,

			"UCLK",
@@ -4061,7 +4061,7 @@ static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) 
			activity_monitor.Mem_PD_Data_error_coeff,

			activity_monitor.Mem_PD_Data_error_rate_coeff);



		size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",

		size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",

			" ",

			3,

			"FCLK",