Commit 0acd1b1c authored by Clark Wang's avatar Clark Wang Committed by Shawn Guo
Browse files

arm64: dts: imx8ulp: increase the clock speed of LPSPI 



LPSPI transfer max speed is half of the root clock.
Increase the root clock speed to support faster data transmission.

And update the parent clock of all i2c/spi with IMX8ULP_CLK_FROSC_DIV2
which could produce accurate clock for i2c/spi usage.

Reviewed-by: default avatarHaibo Chen <haibo.chen@nxp.com>
Reviewed-by: default avatarJun Li <jun.li@nxp.com>
Signed-off-by: default avatarClark Wang <xiaoning.wang@nxp.com>
Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent d2209e65

arch/arm64/boot/dts/freescale/imx8ulp.dtsi

+8 −8
Original line number Diff line number Diff line
@@ -223,7 +223,7 @@ 
					 <&pcc3 IMX8ULP_CLK_LPI2C4>;

				clock-names = "per", "ipg";

				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>;

				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;

				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;

				assigned-clock-rates = <48000000>;

				status = "disabled";

			};
@@ -236,7 +236,7 @@ 
					 <&pcc3 IMX8ULP_CLK_LPI2C5>;

				clock-names = "per", "ipg";

				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>;

				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;

				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;

				assigned-clock-rates = <48000000>;

				status = "disabled";

			};
@@ -269,8 +269,8 @@ 
					 <&pcc3 IMX8ULP_CLK_LPSPI4>;

				clock-names = "per", "ipg";

				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>;

				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;

				assigned-clock-rates = <16000000>;

				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;

				assigned-clock-rates = <48000000>;

				status = "disabled";

			};
@@ -284,8 +284,8 @@ 
					 <&pcc3 IMX8ULP_CLK_LPSPI5>;

				clock-names = "per", "ipg";

				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>;

				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;

				assigned-clock-rates = <16000000>;

				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;

				assigned-clock-rates = <48000000>;

				status = "disabled";

			};

		};
@@ -311,7 +311,7 @@ 
					 <&pcc4 IMX8ULP_CLK_LPI2C6>;

				clock-names = "per", "ipg";

				assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>;

				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;

				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;

				assigned-clock-rates = <48000000>;

				status = "disabled";

			};
@@ -324,7 +324,7 @@ 
					 <&pcc4 IMX8ULP_CLK_LPI2C7>;

				clock-names = "per", "ipg";

				assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>;

				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;

				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;

				assigned-clock-rates = <48000000>;

				status = "disabled";

			};