Unverified Commit 0ab269ed authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!11081 Backport LTS conflicting patches 

Merge Pull Request from: @ci-robot 
 
PR sync from: Peng Zhang <zhangpeng362@huawei.com>
https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/KESQW7ASTXR3FL73DZV6IB6P7LRR5YU2/ 
From: ZhangPeng <zhangpeng362@huawei.com>

Backport v6.6.34-40 LTS conflicting patches for OLK-6.6.

Ajrat Makhmutov (1):
  ALSA: hda/realtek: Enable headset mic on IdeaPad 330-17IKB 81DM

Alex Williamson (2):
  vfio/pci: Collect hot-reset devices to local buffer
  vfio/pci: Restore zero affected bus reset devices warning

Ilpo Järvinen (1):
  EDAC/amd64: Convert PCIBIOS_* return codes to errnos

Karthikeyan Ramasubramanian (1):
  platform/chrome: cros_ec: Handle events during suspend after resume
    completion

Takashi Iwai (1):
  ALSA: hda/realtek: Fix conflicting quirk for PCI SSID 17aa:3820

Yao Xingtao (1):
  cxl/region: check interleave capability

Yi Liu (1):
  vfio/pci: Init the count variable in collecting hot-reset devices


-- 
2.25.1
 
https://gitee.com/openeuler/kernel/issues/IAD6H2 
 
Link:https://gitee.com/openeuler/kernel/pulls/11081

 

Reviewed-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parents 1bd33bfb 952d301b

drivers/cxl/core/hdm.c

+13 −0
Original line number Diff line number Diff line
@@ -52,6 +52,14 @@ int devm_cxl_add_passthrough_decoder(struct cxl_port *port) 
	struct cxl_dport *dport = NULL;

	int single_port_map[1];

	unsigned long index;

	struct cxl_hdm *cxlhdm = dev_get_drvdata(&port->dev);



	/*

	 * Capability checks are moot for passthrough decoders, support

	 * any and all possibilities.

	 */

	cxlhdm->interleave_mask = ~0U;

	cxlhdm->iw_cap_mask = ~0UL;



	cxlsd = cxl_switch_decoder_alloc(port, 1);

	if (IS_ERR(cxlsd))
@@ -79,6 +87,11 @@ static void parse_hdm_decoder_caps(struct cxl_hdm *cxlhdm) 
		cxlhdm->interleave_mask |= GENMASK(11, 8);

	if (FIELD_GET(CXL_HDM_DECODER_INTERLEAVE_14_12, hdm_cap))

		cxlhdm->interleave_mask |= GENMASK(14, 12);

	cxlhdm->iw_cap_mask = BIT(1) | BIT(2) | BIT(4) | BIT(8);

	if (FIELD_GET(CXL_HDM_DECODER_INTERLEAVE_3_6_12_WAY, hdm_cap))

		cxlhdm->iw_cap_mask |= BIT(3) | BIT(6) | BIT(12);

	if (FIELD_GET(CXL_HDM_DECODER_INTERLEAVE_16_WAY, hdm_cap))

		cxlhdm->iw_cap_mask |= BIT(16);

}



static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info)

drivers/cxl/core/region.c

+82 −0
Original line number Diff line number Diff line
@@ -997,6 +997,26 @@ static int cxl_port_attach_region(struct cxl_port *port, 
	}

	cxld = cxl_rr->decoder;



	/*

	 * the number of targets should not exceed the target_count

	 * of the decoder

	 */

	if (is_switch_decoder(&cxld->dev)) {

		struct cxl_switch_decoder *cxlsd;



		cxlsd = to_cxl_switch_decoder(&cxld->dev);

		if (cxl_rr->nr_targets > cxlsd->nr_targets) {

			dev_dbg(&cxlr->dev,

				"%s:%s %s add: %s:%s @ %d overflows targets: %d\n",

				dev_name(port->uport_dev), dev_name(&port->dev),

				dev_name(&cxld->dev), dev_name(&cxlmd->dev),

				dev_name(&cxled->cxld.dev), pos,

				cxlsd->nr_targets);

			rc = -ENXIO;

			goto out_erase;

		}

	}



	rc = cxl_rr_ep_add(cxl_rr, cxled);

	if (rc) {

		dev_dbg(&cxlr->dev,
@@ -1106,6 +1126,50 @@ static int check_last_peer(struct cxl_endpoint_decoder *cxled, 
	return 0;

}



static int check_interleave_cap(struct cxl_decoder *cxld, int iw, int ig)

{

	struct cxl_port *port = to_cxl_port(cxld->dev.parent);

	struct cxl_hdm *cxlhdm = dev_get_drvdata(&port->dev);

	unsigned int interleave_mask;

	u8 eiw;

	u16 eig;

	int high_pos, low_pos;



	if (!test_bit(iw, &cxlhdm->iw_cap_mask))

		return -ENXIO;

	/*

	 * Per CXL specification r3.1(8.2.4.20.13 Decoder Protection),

	 * if eiw < 8:

	 *   DPAOFFSET[51: eig + 8] = HPAOFFSET[51: eig + 8 + eiw]

	 *   DPAOFFSET[eig + 7: 0]  = HPAOFFSET[eig + 7: 0]

	 *

	 *   when the eiw is 0, all the bits of HPAOFFSET[51: 0] are used, the

	 *   interleave bits are none.

	 *

	 * if eiw >= 8:

	 *   DPAOFFSET[51: eig + 8] = HPAOFFSET[51: eig + eiw] / 3

	 *   DPAOFFSET[eig + 7: 0]  = HPAOFFSET[eig + 7: 0]

	 *

	 *   when the eiw is 8, all the bits of HPAOFFSET[51: 0] are used, the

	 *   interleave bits are none.

	 */

	ways_to_eiw(iw, &eiw);

	if (eiw == 0 || eiw == 8)

		return 0;



	granularity_to_eig(ig, &eig);

	if (eiw > 8)

		high_pos = eiw + eig - 1;

	else

		high_pos = eiw + eig + 7;

	low_pos = eig + 8;

	interleave_mask = GENMASK(high_pos, low_pos);

	if (interleave_mask & ~cxlhdm->interleave_mask)

		return -ENXIO;



	return 0;

}



static int cxl_port_setup_targets(struct cxl_port *port,

				  struct cxl_region *cxlr,

				  struct cxl_endpoint_decoder *cxled)
@@ -1256,6 +1320,15 @@ static int cxl_port_setup_targets(struct cxl_port *port, 
			return -ENXIO;

		}

	} else {

		rc = check_interleave_cap(cxld, iw, ig);

		if (rc) {

			dev_dbg(&cxlr->dev,

				"%s:%s iw: %d ig: %d is not supported\n",

				dev_name(port->uport_dev),

				dev_name(&port->dev), iw, ig);

			return rc;

		}



		cxld->interleave_ways = iw;

		cxld->interleave_granularity = ig;

		cxld->hpa_range = (struct range) {
@@ -1692,6 +1765,15 @@ static int cxl_region_attach(struct cxl_region *cxlr, 
	struct cxl_dport *dport;

	int rc = -ENXIO;



	rc = check_interleave_cap(&cxled->cxld, p->interleave_ways,

				  p->interleave_granularity);

	if (rc) {

		dev_dbg(&cxlr->dev, "%s iw: %d ig: %d is not supported\n",

			dev_name(&cxled->cxld.dev), p->interleave_ways,

			p->interleave_granularity);

		return rc;

	}



	if (cxled->mode != cxlr->mode) {

		dev_dbg(&cxlr->dev, "%s region mode: %d mismatch: %d\n",

			dev_name(&cxled->cxld.dev), cxlr->mode, cxled->mode);

drivers/cxl/cxl.h

+2 −0
Original line number Diff line number Diff line
@@ -43,6 +43,8 @@ 
#define   CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4)

#define   CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8)

#define   CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9)

#define   CXL_HDM_DECODER_INTERLEAVE_3_6_12_WAY BIT(11)

#define   CXL_HDM_DECODER_INTERLEAVE_16_WAY BIT(12)

#define CXL_HDM_DECODER_CTRL_OFFSET 0x4

#define   CXL_HDM_DECODER_ENABLE BIT(1)

#define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10)

drivers/cxl/cxlmem.h

+10 −0
Original line number Diff line number Diff line
@@ -888,11 +888,21 @@ static inline void cxl_mem_active_dec(void) 


int cxl_mem_sanitize(struct cxl_memdev *cxlmd, u16 cmd);



/**

 * struct cxl_hdm - HDM Decoder registers and cached / decoded capabilities

 * @regs: mapped registers, see devm_cxl_setup_hdm()

 * @decoder_count: number of decoders for this port

 * @target_count: for switch decoders, max downstream port targets

 * @interleave_mask: interleave granularity capability, see check_interleave_cap()

 * @iw_cap_mask: bitmask of supported interleave ways, see check_interleave_cap()

 * @port: mapped cxl_port, see devm_cxl_setup_hdm()

 */

struct cxl_hdm {

	struct cxl_component_regs regs;

	unsigned int decoder_count;

	unsigned int target_count;

	unsigned int interleave_mask;

	unsigned long iw_cap_mask;

	struct cxl_port *port;

};

drivers/edac/amd64_edac.c

+5 −3
Original line number Diff line number Diff line
@@ -80,7 +80,7 @@ int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset, 
		amd64_warn("%s: error reading F%dx%03x.\n",

			   func, PCI_FUNC(pdev->devfn), offset);



	return err;

	return pcibios_err_to_errno(err);

}



int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
@@ -93,7 +93,7 @@ int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset, 
		amd64_warn("%s: error writing to F%dx%03x.\n",

			   func, PCI_FUNC(pdev->devfn), offset);



	return err;

	return pcibios_err_to_errno(err);

}



static u32 get_umc_base_f18h_m4h(u16 node, u8 channel)
@@ -1027,8 +1027,10 @@ static int gpu_get_node_map(void) 
	}



	ret = pci_read_config_dword(pdev, REG_LOCAL_NODE_TYPE_MAP, &tmp);

	if (ret)

	if (ret) {

		ret = pcibios_err_to_errno(ret);

		goto out;

	}



	gpu_node_map.node_count = FIELD_GET(LNTM_NODE_COUNT, tmp);

	gpu_node_map.base_node_id = FIELD_GET(LNTM_BASE_NODE_ID, tmp);