Commit 0aa25160 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'dmaengine-5.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine 

Pull dmaengine updates from Vinod Koul:
 "New drivers/devices
   - Support for Renesas RZ/G2L dma controller
   - New driver for AMD PTDMA controller

  Updates:
   - Big pile of idxd updates
   - Updates for Altera driver, stm32-dma, dw etc"

* tag 'dmaengine-5.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (83 commits)
  dmaengine: sh: fix some NULL dereferences
  dmaengine: sh: Fix unused initialization of pointer lmdesc
  MAINTAINERS: Fix AMD PTDMA DRIVER entry
  dmaengine: ptdma: remove PT_OFFSET to avoid redefnition
  dmaengine: ptdma: Add debugfs entries for PTDMA
  dmaengine: ptdma: register PTDMA controller as a DMA resource
  dmaengine: ptdma: Initial driver for the AMD PTDMA
  dmaengine: fsl-dpaa2-qdma: Fix spelling mistake "faile" -> "failed"
  dmaengine: idxd: remove interrupt disable for dev_lock
  dmaengine: idxd: remove interrupt disable for cmd_lock
  dmaengine: idxd: fix setting up priv mode for dwq
  dmaengine: xilinx_dma: Set DMA mask for coherent APIs
  dmaengine: ti: k3-psil-j721e: Add entry for CSI2RX
  dmaengine: sh: Add DMAC driver for RZ/G2L SoC
  dmaengine: Extend the dma_slave_width for 128 bytes
  dt-bindings: dma: Document RZ/G2L bindings
  dmaengine: ioat: depends on !UML
  dmaengine: idxd: set descriptor allocation size to threshold for swq
  dmaengine: idxd: make submit failure path consistent on desc freeing
  dmaengine: idxd: remove interrupt flag for completion list spinlock
  ...
parents a3fa7a10 11a427be

Documentation/ABI/stable/sysfs-driver-dma-idxd

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Original line number Diff line number Diff line
@@ -128,6 +128,8 @@ Date: Aug 28, 2020 
KernelVersion:	5.10.0

Contact:	dmaengine@vger.kernel.org

Description:	The last executed device administrative command's status/error.

		Also last configuration error overloaded.

		Writing to it will clear the status.



What:		/sys/bus/dsa/devices/wq<m>.<n>/block_on_fault

Date:		Oct 27, 2020
@@ -211,6 +213,13 @@ Contact: dmaengine@vger.kernel.org 
Description:	Indicate whether ATS disable is turned on for the workqueue.

		0 indicates ATS is on, and 1 indicates ATS is off for the workqueue.



What:		/sys/bus/dsa/devices/wq<m>.<n>/occupancy

Date		May 25, 2021

KernelVersion:	5.14.0

Contact:	dmaengine@vger.kernel.org

Description:	Show the current number of entries in this WQ if WQ Occupancy

		Support bit WQ capabilities is 1.



What:           /sys/bus/dsa/devices/engine<m>.<n>/group_id

Date:           Oct 25, 2019

KernelVersion:  5.6.0

Documentation/admin-guide/kernel-parameters.txt

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Original line number Diff line number Diff line
@@ -1758,6 +1758,11 @@ 
			support for the idxd driver. By default it is set to

			true (1).



	idxd.tc_override= [HW]

			Format: <bool>

			Allow override of default traffic class configuration

			for the device. By default it is set to false (0).



	ieee754=	[MIPS] Select IEEE Std 754 conformance mode

			Format: { strict | legacy | 2008 | relaxed }

			Default: strict

Documentation/devicetree/bindings/dma/altr,msgdma.yaml

+3 −1
Original line number Diff line number Diff line
@@ -24,13 +24,15 @@ properties: 
    items:

      - description: Control and Status Register Slave Port

      - description: Descriptor Slave Port

      - description: Response Slave Port

      - description: Response Slave Port (Optional)

    minItems: 2



  reg-names:

    items:

      - const: csr

      - const: desc

      - const: resp

    minItems: 2



  interrupts:

    maxItems: 1

Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml

0 → 100644
+130 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas RZ/G2L DMA Controller



maintainers:

  - Biju Das <biju.das.jz@bp.renesas.com>



allOf:

  - $ref: "dma-controller.yaml#"



properties:

  compatible:

    items:

      - enum:

          - renesas,r9a07g044-dmac # RZ/G2{L,LC}

      - const: renesas,rz-dmac



  reg:

    items:

      - description: Control and channel register block

      - description: DMA extended resource selector block



  interrupts:

    maxItems: 17



  interrupt-names:

    items:

      - const: error

      - const: ch0

      - const: ch1

      - const: ch2

      - const: ch3

      - const: ch4

      - const: ch5

      - const: ch6

      - const: ch7

      - const: ch8

      - const: ch9

      - const: ch10

      - const: ch11

      - const: ch12

      - const: ch13

      - const: ch14

      - const: ch15



  clocks:

    items:

      - description: DMA main clock

      - description: DMA register access clock



  '#dma-cells':

    const: 1

    description:

      The cell specifies the encoded MID/RID values of the DMAC port

      connected to the DMA client and the slave channel configuration

      parameters.

      bits[0:9] - Specifies MID/RID value

      bit[10] - Specifies DMA request high enable (HIEN)

      bit[11] - Specifies DMA request detection type (LVL)

      bits[12:14] - Specifies DMAACK output mode (AM)

      bit[15] - Specifies Transfer Mode (TM)



  dma-channels:

    const: 16



  power-domains:

    maxItems: 1



  resets:

    items:

      - description: Reset for DMA ARESETN reset terminal

      - description: Reset for DMA RST_ASYNC reset terminal



required:

  - compatible

  - reg

  - interrupts

  - interrupt-names

  - clocks

  - '#dma-cells'

  - dma-channels

  - power-domains

  - resets



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/clock/r9a07g044-cpg.h>



    dmac: dma-controller@11820000 {

        compatible = "renesas,r9a07g044-dmac",

                     "renesas,rz-dmac";

        reg = <0x11820000 0x10000>,

              <0x11830000 0x10000>;

        interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,

                     <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,

                     <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,

                     <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,

                     <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,

                     <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,

                     <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,

                     <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,

                     <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,

                     <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,

                     <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,

                     <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,

                     <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,

                     <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,

                     <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,

                     <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,

                     <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;

        interrupt-names = "error",

                          "ch0", "ch1", "ch2", "ch3",

                          "ch4", "ch5", "ch6", "ch7",

                          "ch8", "ch9", "ch10", "ch11",

                          "ch12", "ch13", "ch14", "ch15";

        clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,

                 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;

        power-domains = <&cpg>;

        resets = <&cpg R9A07G044_DMAC_ARESETN>,

                 <&cpg R9A07G044_DMAC_RST_ASYNC>;

        #dma-cells = <1>;

        dma-channels = <16>;

    };

Documentation/devicetree/bindings/dma/st,stm32-dma.yaml

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@@ -40,6 +40,13 @@ description: | 
         0x0: FIFO mode with threshold selectable with bit 0-1

         0x1: Direct mode: each DMA request immediately initiates a transfer

              from/to the memory, FIFO is bypassed.

       -bit 4: alternative DMA request/acknowledge protocol

         0x0: Use standard DMA ACK management, where ACK signal is maintained

              up to the removal of request and transfer completion

         0x1: Use alternative DMA ACK management, where ACK de-assertion does

              not wait for the de-assertion of the REQuest, ACK is only managed

              by transfer completion. This must only be used on channels

              managing transfers for STM32 USART/UART.





maintainers: