drm/i915/guc: Keep strict GuC ABI definitions (0a8e247d) · Commits · EulixOS / Software / Kernel

drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h

0 → 100644

+51 −0

Original line number	Diff line number	Diff line
		/* SPDX-License-Identifier: MIT */
		/*
		* Copyright © 2014-2021 Intel Corporation
		*/

		#ifndef _ABI_GUC_ACTIONS_ABI_H
		#define _ABI_GUC_ACTIONS_ABI_H

		enum intel_guc_action {
		INTEL_GUC_ACTION_DEFAULT = 0x0,
		INTEL_GUC_ACTION_REQUEST_PREEMPTION = 0x2,
		INTEL_GUC_ACTION_REQUEST_ENGINE_RESET = 0x3,
		INTEL_GUC_ACTION_ALLOCATE_DOORBELL = 0x10,
		INTEL_GUC_ACTION_DEALLOCATE_DOORBELL = 0x20,
		INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30,
		INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x40,
		INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 0x302,
		INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,
		INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
		INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
		INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
		INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505,
		INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506,
		INTEL_GUC_ACTION_LIMIT
		};

		enum intel_guc_preempt_options {
		INTEL_GUC_PREEMPT_OPTION_DROP_WORK_Q = 0x4,
		INTEL_GUC_PREEMPT_OPTION_DROP_SUBMIT_Q = 0x8,
		};

		enum intel_guc_report_status {
		INTEL_GUC_REPORT_STATUS_UNKNOWN = 0x0,
		INTEL_GUC_REPORT_STATUS_ACKED = 0x1,
		INTEL_GUC_REPORT_STATUS_ERROR = 0x2,
		INTEL_GUC_REPORT_STATUS_COMPLETE = 0x4,
		};

		enum intel_guc_sleep_state_status {
		INTEL_GUC_SLEEP_STATE_SUCCESS = 0x1,
		INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x2,
		INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x3
		#define INTEL_GUC_SLEEP_STATE_INVALID_MASK 0x80000000
		};

		#define GUC_LOG_CONTROL_LOGGING_ENABLED (1 << 0)
		#define GUC_LOG_CONTROL_VERBOSITY_SHIFT 4
		#define GUC_LOG_CONTROL_VERBOSITY_MASK (0xF << GUC_LOG_CONTROL_VERBOSITY_SHIFT)
		#define GUC_LOG_CONTROL_DEFAULT_LOGGING (1 << 8)

		#endif /* _ABI_GUC_ACTIONS_ABI_H */

drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h

0 → 100644

+106 −0

Original line number	Diff line number	Diff line
		/* SPDX-License-Identifier: MIT */
		/*
		* Copyright © 2014-2021 Intel Corporation
		*/

		#ifndef _ABI_GUC_COMMUNICATION_CTB_ABI_H
		#define _ABI_GUC_COMMUNICATION_CTB_ABI_H

		#include <linux/types.h>

		/**
		* DOC: CTB based communication
		*
		* The CTB (command transport buffer) communication between Host and GuC
		* is based on u32 data stream written to the shared buffer. One buffer can
		* be used to transmit data only in one direction (one-directional channel).
		*
		* Current status of the each buffer is stored in the buffer descriptor.
		* Buffer descriptor holds tail and head fields that represents active data
		* stream. The tail field is updated by the data producer (sender), and head
		* field is updated by the data consumer (receiver)::
		*
		* +------------+
		* \| DESCRIPTOR \| +=================+============+========+
		* +============+ \| \| MESSAGE(s) \| \|
		* \| address \|--------->+=================+============+========+
		* +------------+
		* \| head \| ^-----head--------^
		* +------------+
		* \| tail \| ^---------tail-----------------^
		* +------------+
		* \| size \| ^---------------size--------------------^
		* +------------+
		*
		* Each message in data stream starts with the single u32 treated as a header,
		* followed by optional set of u32 data that makes message specific payload::
		*
		* +------------+---------+---------+---------+
		* \| MESSAGE \|
		* +------------+---------+---------+---------+
		* \| msg[0] \| [1] \| ... \| [n-1] \|
		* +------------+---------+---------+---------+
		* \| MESSAGE \| MESSAGE PAYLOAD \|
		* + HEADER +---------+---------+---------+
		* \| \| 0 \| ... \| n \|
		* +======+=====+=========+=========+=========+
		* \| 31:16\| code\| \| \| \|
		* +------+-----+ \| \| \|
		* \| 15:5\|flags\| \| \| \|
		* +------+-----+ \| \| \|
		* \| 4:0\| len\| \| \| \|
		* +------+-----+---------+---------+---------+
		*
		* ^-------------len-------------^
		*
		* The message header consists of:
		*
		* - len, indicates length of the message payload (in u32)
		* - code, indicates message code
		* - flags, holds various bits to control message handling
		*/

		/*
		* Describes single command transport buffer.
		* Used by both guc-master and clients.
		*/
		struct guc_ct_buffer_desc {
		u32 addr; /* gfx address */
		u64 host_private; /* host private data */
		u32 size; /* size in bytes */
		u32 head; /* offset updated by GuC*/
		u32 tail; /* offset updated by owner */
		u32 is_in_error; /* error indicator */
		u32 fence; /* fence updated by GuC */
		u32 status; /* status updated by GuC */
		u32 owner; /* id of the channel owner */
		u32 owner_sub_id; /* owner-defined field for extra tracking */
		u32 reserved[5];
		} __packed;

		/* Type of command transport buffer */
		#define INTEL_GUC_CT_BUFFER_TYPE_SEND 0x0u
		#define INTEL_GUC_CT_BUFFER_TYPE_RECV 0x1u

		/*
		* Definition of the command transport message header (DW0)
		*
		* bit[4..0] message len (in dwords)
		* bit[7..5] reserved
		* bit[8] response (G2H only)
		* bit[8] write fence to desc (H2G only)
		* bit[9] write status to H2G buff (H2G only)
		* bit[10] send status back via G2H (H2G only)
		* bit[15..11] reserved
		* bit[31..16] action code
		*/
		#define GUC_CT_MSG_LEN_SHIFT 0
		#define GUC_CT_MSG_LEN_MASK 0x1F
		#define GUC_CT_MSG_IS_RESPONSE (1 << 8)
		#define GUC_CT_MSG_WRITE_FENCE_TO_DESC (1 << 8)
		#define GUC_CT_MSG_WRITE_STATUS_TO_BUFF (1 << 9)
		#define GUC_CT_MSG_SEND_STATUS (1 << 10)
		#define GUC_CT_MSG_ACTION_SHIFT 16
		#define GUC_CT_MSG_ACTION_MASK 0xFFFF

		#endif /* _ABI_GUC_COMMUNICATION_CTB_ABI_H */

drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h

0 → 100644

+52 −0

Original line number	Diff line number	Diff line
		/* SPDX-License-Identifier: MIT */
		/*
		* Copyright © 2014-2021 Intel Corporation
		*/

		#ifndef _ABI_GUC_COMMUNICATION_MMIO_ABI_H
		#define _ABI_GUC_COMMUNICATION_MMIO_ABI_H

		/**
		* DOC: MMIO based communication
		*
		* The MMIO based communication between Host and GuC uses software scratch
		* registers, where first register holds data treated as message header,
		* and other registers are used to hold message payload.
		*
		* For Gen9+, GuC uses software scratch registers 0xC180-0xC1B8,
		* but no H2G command takes more than 8 parameters and the GuC FW
		* itself uses an 8-element array to store the H2G message.
		*
		* +-----------+---------+---------+---------+
		* \| MMIO[0] \| MMIO[1] \| ... \| MMIO[n] \|
		* +-----------+---------+---------+---------+
		* \| header \| optional payload \|
		* +======+====+=========+=========+=========+
		* \| 31:28\|type\| \| \| \|
		* +------+----+ \| \| \|
		* \| 27:16\|data\| \| \| \|
		* +------+----+ \| \| \|
		* \| 15:0\|code\| \| \| \|
		* +------+----+---------+---------+---------+
		*
		* The message header consists of:
		*
		* - type, indicates message type
		* - code, indicates message code, is specific for type
		* - data, indicates message data, optional, depends on code
		*
		* The following message types are supported:
		*
		* - REQUEST, indicates Host-to-GuC request, requested GuC action code
		* must be priovided in code field. Optional action specific parameters
		* can be provided in remaining payload registers or data field.
		*
		* - RESPONSE, indicates GuC-to-Host response from earlier GuC request,
		* action response status will be provided in code field. Optional
		* response data can be returned in remaining payload registers or data
		* field.
		*/

		#define GUC_MAX_MMIO_MSG_LEN 8

		#endif /* _ABI_GUC_COMMUNICATION_MMIO_ABI_H */

drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h

0 → 100644

+14 −0

Original line number	Diff line number	Diff line
		/* SPDX-License-Identifier: MIT */
		/*
		* Copyright © 2014-2021 Intel Corporation
		*/

		#ifndef _ABI_GUC_ERRORS_ABI_H
		#define _ABI_GUC_ERRORS_ABI_H

		enum intel_guc_response_status {
		INTEL_GUC_RESPONSE_STATUS_SUCCESS = 0x0,
		INTEL_GUC_RESPONSE_STATUS_GENERIC_FAIL = 0xF000,
		};

		#endif /* _ABI_GUC_ERRORS_ABI_H */

drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h

0 → 100644

+21 −0

Original line number	Diff line number	Diff line
		/* SPDX-License-Identifier: MIT */
		/*
		* Copyright © 2014-2021 Intel Corporation
		*/

		#ifndef _ABI_GUC_MESSAGES_ABI_H
		#define _ABI_GUC_MESSAGES_ABI_H

		#define INTEL_GUC_MSG_TYPE_SHIFT 28
		#define INTEL_GUC_MSG_TYPE_MASK (0xF << INTEL_GUC_MSG_TYPE_SHIFT)
		#define INTEL_GUC_MSG_DATA_SHIFT 16
		#define INTEL_GUC_MSG_DATA_MASK (0xFFF << INTEL_GUC_MSG_DATA_SHIFT)
		#define INTEL_GUC_MSG_CODE_SHIFT 0
		#define INTEL_GUC_MSG_CODE_MASK (0xFFFF << INTEL_GUC_MSG_CODE_SHIFT)

		enum intel_guc_msg_type {
		INTEL_GUC_MSG_TYPE_REQUEST = 0x0,
		INTEL_GUC_MSG_TYPE_RESPONSE = 0xF,
		};

		#endif /* _ABI_GUC_MESSAGES_ABI_H */