Unverified Commit 0a3381a0 authored Jun 05, 2023 by Greentime Hu Committed by Palmer Dabbelt Jun 08, 2023

riscv: Introduce Vector enable/disable helpers



These are small and likely to be frequently called so implement as
inline routines (vs. function call).

Co-developed-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Co-developed-by: Vincent Chen <vincent.chen@sifive.com>
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Tested-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/20230605110724.21391-8-andy.chiu@sifive.com


Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

parent 74abe5a3

arch/riscv/include/asm/vector.h

+11 −0

Original line number	Diff line number	Diff line
		@@ -11,12 +11,23 @@
		#ifdef CONFIG_RISCV_ISA_V

		#include <asm/hwcap.h>
		#include <asm/csr.h>

		static __always_inline bool has_vector(void)
		{
		return riscv_has_extension_unlikely(RISCV_ISA_EXT_v);
		}

		static __always_inline void riscv_v_enable(void)
		{
		csr_set(CSR_SSTATUS, SR_VS);
		}

		static __always_inline void riscv_v_disable(void)
		{
		csr_clear(CSR_SSTATUS, SR_VS);
		}

		#else /* ! CONFIG_RISCV_ISA_V */

		static __always_inline bool has_vector(void) { return false; }