Unverified Commit 0a047daf authored by Peter Ujfalusi's avatar Peter Ujfalusi Committed by Mark Brown
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ASoC: SOF: ipc3: Add set_core_state pm_ops implementation 



IPC3 uses sof_ipc_pm_core_config message
(SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CORE_ENABLE) to enable/disable cores
managed by the DSP.
The core state is set via a single bitfield, if the bit is 1 the core
should be on, if it is 0 then it is off.

Signed-off-by: default avatarPeter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: default avatarRanjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: default avatarBard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20220610083549.16773-4-peter.ujfalusi@linux.intel.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent b41252d8

sound/soc/sof/ipc3.c

+18 −0
Original line number Diff line number Diff line
@@ -1037,6 +1037,23 @@ static void sof_ipc3_rx_msg(struct snd_sof_dev *sdev) 
	ipc3_log_header(sdev->dev, "ipc rx done", hdr.cmd);

}



static int sof_ipc3_set_core_state(struct snd_sof_dev *sdev, int core_idx, bool on)

{

	struct sof_ipc_pm_core_config core_cfg = {

		.hdr.size = sizeof(core_cfg),

		.hdr.cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CORE_ENABLE,

	};

	struct sof_ipc_reply reply;



	if (on)

		core_cfg.enable_mask = sdev->enabled_cores_mask | BIT(core_idx);

	else

		core_cfg.enable_mask = sdev->enabled_cores_mask & ~BIT(core_idx);



	return sof_ipc3_tx_msg(sdev, &core_cfg, sizeof(core_cfg),

			       &reply, sizeof(reply), false);

}



static int sof_ipc3_ctx_ipc(struct snd_sof_dev *sdev, int cmd)

{

	struct sof_ipc_pm_ctx pm_ctx = {
@@ -1063,6 +1080,7 @@ static int sof_ipc3_ctx_restore(struct snd_sof_dev *sdev) 
static const struct sof_ipc_pm_ops ipc3_pm_ops = {

	.ctx_save = sof_ipc3_ctx_save,

	.ctx_restore = sof_ipc3_ctx_restore,

	.set_core_state = sof_ipc3_set_core_state,

};



const struct sof_ipc_ops ipc3_ops = {