Unverified Commit 09f85289 authored by Mark Brown's avatar Mark Brown
Browse files

ASoC: SOF: mediatek: fix boot sequences 

Merge series from Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>:

Changes to DSP_RESET_SW need extra care.
parents 2d86cef3 99bad468

sound/soc/sof/mediatek/mt8195/mt8195-loader.c

+9 −4
Original line number Diff line number Diff line
@@ -21,7 +21,7 @@ void sof_hifixdsp_boot_sequence(struct snd_sof_dev *sdev, u32 boot_addr) 


	/* pull high StatVectorSel to use AltResetVec (set bit4 to 1) */

	snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW,

				DSP_RESET_SW, DSP_RESET_SW);

				STATVECTOR_SEL, STATVECTOR_SEL);



	/* toggle  DReset & BReset */

	/* pull high DReset & BReset */
@@ -29,6 +29,9 @@ void sof_hifixdsp_boot_sequence(struct snd_sof_dev *sdev, u32 boot_addr) 
				ADSP_BRESET_SW | ADSP_DRESET_SW,

				ADSP_BRESET_SW | ADSP_DRESET_SW);



	/* delay 10 DSP cycles at 26M about 1us by IP vendor's suggestion */

	udelay(1);



	/* pull low DReset & BReset */

	snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW,

				ADSP_BRESET_SW | ADSP_DRESET_SW,
@@ -46,11 +49,13 @@ void sof_hifixdsp_boot_sequence(struct snd_sof_dev *sdev, u32 boot_addr) 


void sof_hifixdsp_shutdown(struct snd_sof_dev *sdev)

{

	/* Clear to 0 firstly */

	snd_sof_dsp_write(sdev, DSP_REG_BAR, DSP_RESET_SW, 0x0);



	/* RUN_STALL pull high again to reset */

	snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW,

				ADSP_RUNSTALL, ADSP_RUNSTALL);



	/* pull high DReset & BReset */

	snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW,

				ADSP_BRESET_SW | ADSP_DRESET_SW,

				ADSP_BRESET_SW | ADSP_DRESET_SW);

}