Commit 09f82b06 authored by Ravi Bangoria's avatar Ravi Bangoria Committed by Michael Ellerman
Browse files

powerpc/watchpoint: Rename current DAWR macros 



Power10 is introducing second DAWR. Use real register names from ISA
for current macros:
  s/SPRN_DAWR/SPRN_DAWR0/
  s/SPRN_DAWRX/SPRN_DAWRX0/

Signed-off-by: default avatarRavi Bangoria <ravi.bangoria@linux.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Reviewed-by: default avatarMichael Neuling <mikey@neuling.org>
Link: https://lore.kernel.org/r/20200514111741.97993-2-ravi.bangoria@linux.ibm.com
parent 3920742b

arch/powerpc/include/asm/reg.h

+2 −2
Original line number Diff line number Diff line
@@ -283,14 +283,14 @@ 
#define   CTRL_CT1	0x40000000	/* thread 1 */

#define   CTRL_TE	0x00c00000	/* thread enable */

#define   CTRL_RUNLATCH	0x1

#define SPRN_DAWR	0xB4

#define SPRN_DAWR0	0xB4

#define SPRN_RPR	0xBA	/* Relative Priority Register */

#define SPRN_CIABR	0xBB

#define   CIABR_PRIV		0x3

#define   CIABR_PRIV_USER	1

#define   CIABR_PRIV_SUPER	2

#define   CIABR_PRIV_HYPER	3

#define SPRN_DAWRX	0xBC

#define SPRN_DAWRX0	0xBC

#define   DAWRX_USER	__MASK(0)

#define   DAWRX_KERNEL	__MASK(1)

#define   DAWRX_HYP	__MASK(2)

arch/powerpc/kernel/dawr.c

+2 −2
Original line number Diff line number Diff line
@@ -39,8 +39,8 @@ int set_dawr(struct arch_hw_breakpoint *brk) 
	if (ppc_md.set_dawr)

		return ppc_md.set_dawr(dawr, dawrx);



	mtspr(SPRN_DAWR, dawr);

	mtspr(SPRN_DAWRX, dawrx);

	mtspr(SPRN_DAWR0, dawr);

	mtspr(SPRN_DAWRX0, dawrx);



	return 0;

}

arch/powerpc/kvm/book3s_hv.c

+6 −6
Original line number Diff line number Diff line
@@ -3392,8 +3392,8 @@ static int kvmhv_load_hv_regs_and_go(struct kvm_vcpu *vcpu, u64 time_limit, 
	int trap;

	unsigned long host_hfscr = mfspr(SPRN_HFSCR);

	unsigned long host_ciabr = mfspr(SPRN_CIABR);

	unsigned long host_dawr = mfspr(SPRN_DAWR);

	unsigned long host_dawrx = mfspr(SPRN_DAWRX);

	unsigned long host_dawr = mfspr(SPRN_DAWR0);

	unsigned long host_dawrx = mfspr(SPRN_DAWRX0);

	unsigned long host_psscr = mfspr(SPRN_PSSCR);

	unsigned long host_pidr = mfspr(SPRN_PID);
@@ -3422,8 +3422,8 @@ static int kvmhv_load_hv_regs_and_go(struct kvm_vcpu *vcpu, u64 time_limit, 
	mtspr(SPRN_SPURR, vcpu->arch.spurr);



	if (dawr_enabled()) {

		mtspr(SPRN_DAWR, vcpu->arch.dawr);

		mtspr(SPRN_DAWRX, vcpu->arch.dawrx);

		mtspr(SPRN_DAWR0, vcpu->arch.dawr);

		mtspr(SPRN_DAWRX0, vcpu->arch.dawrx);

	}

	mtspr(SPRN_CIABR, vcpu->arch.ciabr);

	mtspr(SPRN_IC, vcpu->arch.ic);
@@ -3475,8 +3475,8 @@ static int kvmhv_load_hv_regs_and_go(struct kvm_vcpu *vcpu, u64 time_limit, 
	      (local_paca->kvm_hstate.fake_suspend << PSSCR_FAKE_SUSPEND_LG));

	mtspr(SPRN_HFSCR, host_hfscr);

	mtspr(SPRN_CIABR, host_ciabr);

	mtspr(SPRN_DAWR, host_dawr);

	mtspr(SPRN_DAWRX, host_dawrx);

	mtspr(SPRN_DAWR0, host_dawr);

	mtspr(SPRN_DAWRX0, host_dawrx);

	mtspr(SPRN_PID, host_pidr);



	/*

arch/powerpc/kvm/book3s_hv_rmhandlers.S

+9 −9
Original line number Diff line number Diff line
@@ -707,8 +707,8 @@ BEGIN_FTR_SECTION 
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)

BEGIN_FTR_SECTION

	mfspr	r5, SPRN_CIABR

	mfspr	r6, SPRN_DAWR

	mfspr	r7, SPRN_DAWRX

	mfspr	r6, SPRN_DAWR0

	mfspr	r7, SPRN_DAWRX0

	mfspr	r8, SPRN_IAMR

	std	r5, STACK_SLOT_CIABR(r1)

	std	r6, STACK_SLOT_DAWR(r1)
@@ -803,8 +803,8 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) 
	beq	1f

	ld	r5, VCPU_DAWR(r4)

	ld	r6, VCPU_DAWRX(r4)

	mtspr	SPRN_DAWR, r5

	mtspr	SPRN_DAWRX, r6

	mtspr	SPRN_DAWR0, r5

	mtspr	SPRN_DAWRX0, r6

1:

	ld	r7, VCPU_CIABR(r4)

	ld	r8, VCPU_TAR(r4)
@@ -1766,8 +1766,8 @@ BEGIN_FTR_SECTION 
	 * If the DAWR doesn't work, it's ok to write these here as

	 * this value should always be zero

	*/

	mtspr	SPRN_DAWR, r6

	mtspr	SPRN_DAWRX, r7

	mtspr	SPRN_DAWR0, r6

	mtspr	SPRN_DAWRX0, r7

END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)

BEGIN_FTR_SECTION

	ld	r5, STACK_SLOT_TID(r1)
@@ -2577,8 +2577,8 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) 
	mfmsr	r6

	andi.	r6, r6, MSR_DR		/* in real mode? */

	bne	4f

	mtspr	SPRN_DAWR, r4

	mtspr	SPRN_DAWRX, r5

	mtspr	SPRN_DAWR0, r4

	mtspr	SPRN_DAWRX0, r5

4:	li	r3, 0

	blr
@@ -3329,7 +3329,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300) 
	mtspr	SPRN_AMR, r0

	mtspr	SPRN_IAMR, r0

	mtspr	SPRN_CIABR, r0

	mtspr	SPRN_DAWRX, r0

	mtspr	SPRN_DAWRX0, r0



BEGIN_MMU_FTR_SECTION

	b	4f

arch/powerpc/xmon/xmon.c

+1 −1
Original line number Diff line number Diff line
@@ -1956,7 +1956,7 @@ static void dump_207_sprs(void) 
	printf("hfscr  = %.16lx  dhdes = %.16lx rpr    = %.16lx\n",

		mfspr(SPRN_HFSCR), mfspr(SPRN_DHDES), mfspr(SPRN_RPR));

	printf("dawr   = %.16lx  dawrx = %.16lx ciabr  = %.16lx\n",

		mfspr(SPRN_DAWR), mfspr(SPRN_DAWRX), mfspr(SPRN_CIABR));

		mfspr(SPRN_DAWR0), mfspr(SPRN_DAWRX0), mfspr(SPRN_CIABR));

#endif

}