Commit 09d49e14 authored by Jonathan Kim's avatar Jonathan Kim Committed by Alex Deucher
Browse files

drm/amdkfd: fix and enable debugging for gfx11 



There are a couple of fixes required to enable gfx11 debugging.

First, ADD_QUEUE.trap_en is an inappropriate place to toggle
a per-process register so move it to SET_SHADER_DEBUGGER.trap_en.
When ADD_QUEUE.skip_process_ctx_clear is set, MES will prioritize
the SET_SHADER_DEBUGGER.trap_en setting.

Second, to preserve correct save/restore priviledged wave states
in coordination with the trap enablement setting, resume suspended
waves early in the disable call.

Signed-off-by: default avatarJonathan Kim <jonathan.kim@amd.com>
Reviewed-by: default avatarFelix Kuehling <felix.kuehling@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fe56c6ee

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c

+6 −1
Original line number Diff line number Diff line
@@ -928,7 +928,8 @@ int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev, 
				uint64_t process_context_addr,

				uint32_t spi_gdbg_per_vmid_cntl,

				const uint32_t *tcp_watch_cntl,

				uint32_t flags)

				uint32_t flags,

				bool trap_en)

{

	struct mes_misc_op_input op_input = {0};

	int r;
@@ -945,6 +946,10 @@ int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev, 
	memcpy(op_input.set_shader_debugger.tcp_watch_cntl, tcp_watch_cntl,

			sizeof(op_input.set_shader_debugger.tcp_watch_cntl));



	if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >>

			AMDGPU_MES_API_VERSION_SHIFT) >= 14)

		op_input.set_shader_debugger.trap_en = trap_en;



	amdgpu_mes_lock(&adev->mes);



	r = adev->mes.funcs->misc_op(&adev->mes, &op_input);

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h

+3 −1
Original line number Diff line number Diff line
@@ -294,6 +294,7 @@ struct mes_misc_op_input { 
			} flags;

			uint32_t spi_gdbg_per_vmid_cntl;

			uint32_t tcp_watch_cntl[4];

			uint32_t trap_en;

		} set_shader_debugger;

	};

};
@@ -361,7 +362,8 @@ int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev, 
				uint64_t process_context_addr,

				uint32_t spi_gdbg_per_vmid_cntl,

				const uint32_t *tcp_watch_cntl,

				uint32_t flags);

				uint32_t flags,

				bool trap_en);



int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id,

			int queue_type, int idx,

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

+1 −0
Original line number Diff line number Diff line
@@ -347,6 +347,7 @@ static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 
		memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl,

				input->set_shader_debugger.tcp_watch_cntl,

				sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl));

		misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en;

		break;

	default:

		DRM_ERROR("unsupported misc op (%d) \n", input->op);

drivers/gpu/drm/amd/amdkfd/kfd_debug.c

+6 −8
Original line number Diff line number Diff line
@@ -349,12 +349,13 @@ int kfd_dbg_set_mes_debug_mode(struct kfd_process_device *pdd) 
{

	uint32_t spi_dbg_cntl = pdd->spi_dbg_override | pdd->spi_dbg_launch_mode;

	uint32_t flags = pdd->process->dbg_flags;

	bool sq_trap_en = !!spi_dbg_cntl;



	if (!kfd_dbg_is_per_vmid_supported(pdd->dev))

		return 0;



	return amdgpu_mes_set_shader_debugger(pdd->dev->adev, pdd->proc_ctx_gpu_addr, spi_dbg_cntl,

						pdd->watch_points, flags);

						pdd->watch_points, flags, sq_trap_en);

}



#define KFD_DEBUGGER_INVALID_WATCH_POINT_ID -1
@@ -557,6 +558,10 @@ void kfd_dbg_trap_deactivate(struct kfd_process *target, bool unwind, int unwind 


	if (!unwind) {

		uint32_t flags = 0;

		int resume_count = resume_queues(target, 0, NULL);



		if (resume_count)

			pr_debug("Resumed %d queues\n", resume_count);



		cancel_work_sync(&target->debug_event_workarea);

		kfd_dbg_clear_process_address_watch(target);
@@ -598,13 +603,6 @@ void kfd_dbg_trap_deactivate(struct kfd_process *target, bool unwind, int unwind 
	}



	kfd_dbg_set_workaround(target, false);



	if (!unwind) {

		int resume_count = resume_queues(target, 0, NULL);



		if (resume_count)

			pr_debug("Resumed %d queues\n", resume_count);

	}

}



static void kfd_dbg_clean_exception_status(struct kfd_process *target)

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c

+1 −2
Original line number Diff line number Diff line
@@ -227,8 +227,7 @@ static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q, 
	queue_input.tba_addr = qpd->tba_addr;

	queue_input.tma_addr = qpd->tma_addr;

	queue_input.trap_en = KFD_GC_VERSION(q->device) < IP_VERSION(11, 0, 0) ||

			      KFD_GC_VERSION(q->device) >= IP_VERSION(12, 0, 0) ||

			      q->properties.is_dbg_wa;

			      KFD_GC_VERSION(q->device) >= IP_VERSION(12, 0, 0);

	queue_input.skip_process_ctx_clear = qpd->pqm->process->debug_trap_enabled;



	queue_type = convert_to_mes_queue_type(q->properties.type);