Commit 09a8e5f0 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/controller/kconfig' 

- Use uniform language in Kconfig menu entries (Bjorn Helgaas)

- Sort controller Kconfig entries by vendor (Bjorn Helgaas)

* pci/controller/kconfig:
  PCI: xilinx: Drop obsolete dependency on COMPILE_TEST
  PCI: mobiveil: Sort Kconfig entries by vendor
  PCI: dwc: Sort Kconfig entries by vendor
  PCI: Sort controller Kconfig entries by vendor
  PCI: Use consistent controller Kconfig menu entry language
  PCI: xilinx-nwl: Add 'Xilinx' to Kconfig prompt
  PCI: hv: Add 'Microsoft' to Kconfig prompt
  PCI: meson: Add 'Amlogic' to Kconfig prompt
  PCI: Use of_property_present() for testing DT property presence
  PCI/PM: Extend D3hot delay for NVIDIA HDA controllers
  dt-bindings: PCI: qcom: Document msi-map and msi-map-mask properties
  PCI: qcom: Add SM8550 PCIe support
  dt-bindings: PCI: qcom: Add SM8550 compatible
  PCI: qcom: Add support for SDX55 SoC
  dt-bindings: PCI: qcom-ep: Fix the unit address used in example
  dt-bindings: PCI: qcom: Add SDX55 SoC
  dt-bindings: PCI: qcom: Update maintainers entry
  PCI: qcom: Enable async probe by default
  PCI: qcom: Add support for system suspend and resume
  PCI/PM: Drop pci_bridge_wait_for_secondary_bus() timeout parameter
  PCI/PM: Increase wait time after resume
  PCI: pciehp: Fix AB-BA deadlock between reset_lock and device_lock
  PCI: Fix up L1SS capability for Intel Apollo Lake Root Port
  PCI: qcom: Expose link transition counts via debugfs
  dt-bindings: PCI: qcom: Add "mhi" register region to supported SoCs
  PCI: qcom: Rename qcom_pcie_config_sid_sm8250() to reflect IP version
  PCI: qcom: Use macros for defining total no. of clocks & supplies
  PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.4.0
  PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.3.3
  PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.3
  PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.2
  PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 1.0.0
  PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.1.0
  PCI: qcom: Use lower case for hex
  PCI: qcom: Add missing macros for register fields
  PCI: qcom: Use bitfield definitions for register fields
  PCI: qcom: Sort and group registers and bitfield definitions
  PCI: qcom: Remove PCIE20_ prefix from register definitions
  PCI: qcom: Fix the incorrect register usage in v2.7.0 config
  PCI/EDR: Add edr_handle_event() comments
  PCI/EDR: Clear Device Status after EDR error recovery
  efi/cper: Remove unnecessary aer.h include
  dt-bindings: imx6q-pcie: Restruct i.MX PCIe schema
  PCI/P2PDMA: Fix pci_p2pmem_find_many() kernel-doc
  EISA: Drop unused pci_bus_for_each_resource() index argument
  PCI: Make pci_bus_for_each_resource() index optional
  PCI: Document pci_bus_for_each_resource()
  PCI: Introduce pci_dev_for_each_resource()
  PCI: Introduce pci_resource_n()
  PCI: ixp4xx: Use PCI_CONF1_ADDRESS() macro
  PCI: mt7621: Use dev_info() to log PCIe card detection
  PCI: imx6: Install the fault handler only on compatible match
  PCI: layerscape: Add EP mode support for ls1028a
  PCI: rcar: Avoid defines prefixed with CONFIG
  dt-bindings: PCI: convert amlogic,meson-pcie.txt to dt-schema
  PCI: kirin: Select REGMAP_MMIO
parents fe15c26e ab072a3b

.clang-format

+1 −0
Original line number Diff line number Diff line
@@ -520,6 +520,7 @@ ForEachMacros: 
  - 'of_property_for_each_string'

  - 'of_property_for_each_u32'

  - 'pci_bus_for_each_resource'

  - 'pci_dev_for_each_resource'

  - 'pci_doe_for_each_off'

  - 'pcl_for_each_chunk'

  - 'pcl_for_each_segment'

Documentation/devicetree/bindings/pci/amlogic,axg-pcie.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/amlogic,axg-pcie.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Amlogic Meson AXG DWC PCIe SoC controller



maintainers:

  - Neil Armstrong <neil.armstrong@linaro.org>



description:

  Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core.



allOf:

  - $ref: /schemas/pci/pci-bus.yaml#

  - $ref: /schemas/pci/snps,dw-pcie-common.yaml#



# We need a select here so we don't match all nodes with 'snps,dw-pcie'

select:

  properties:

    compatible:

      enum:

        - amlogic,axg-pcie

        - amlogic,g12a-pcie

  required:

    - compatible



properties:

  compatible:

    items:

      - enum:

          - amlogic,axg-pcie

          - amlogic,g12a-pcie

      - const: snps,dw-pcie



  reg:

    items:

      - description: External local bus interface registers

      - description: Meson designed configuration registers

      - description: PCIe configuration space



  reg-names:

    items:

      - const: elbi

      - const: cfg

      - const: config



  interrupts:

    maxItems: 1



  clocks:

    items:

      - description: PCIe GEN 100M PLL clock

      - description: PCIe RC clock gate

      - description: PCIe PHY clock



  clock-names:

    items:

      - const: pclk

      - const: port

      - const: general



  phys:

    maxItems: 1



  phy-names:

    const: pcie



  resets:

    items:

      - description: Port Reset

      - description: Shared APB reset



  reset-names:

    items:

      - const: port

      - const: apb



  num-lanes:

    const: 1



  power-domains:

    maxItems: 1



required:

  - compatible

  - reg

  - reg-names

  - interrupts

  - clock

  - clock-names

  - "#address-cells"

  - "#size-cells"

  - "#interrupt-cells"

  - interrupt-map

  - interrupt-map-mask

  - ranges

  - bus-range

  - device_type

  - num-lanes

  - phys

  - phy-names

  - resets

  - reset-names



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    pcie: pcie@f9800000 {

        compatible = "amlogic,axg-pcie", "snps,dw-pcie";

        reg = <0xf9800000 0x400000>, <0xff646000 0x2000>, <0xf9f00000 0x100000>;

        reg-names = "elbi", "cfg", "config";

        interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;

        clocks = <&pclk>, <&clk_port>, <&clk_phy>;

        clock-names = "pclk", "port", "general";

        resets = <&reset_pcie_port>, <&reset_pcie_apb>;

        reset-names = "port", "apb";

        phys = <&pcie_phy>;

        phy-names = "pcie";

        #interrupt-cells = <1>;

        interrupt-map-mask = <0 0 0 0>;

        interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;

        bus-range = <0x0 0xff>;

        #address-cells = <3>;

        #size-cells = <2>;

        device_type = "pci";

        num-lanes = <1>;

        ranges = <0x82000000 0 0 0xf9c00000 0 0x00300000>;

    };

...

Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt

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Amlogic Meson AXG DWC PCIE SoC controller



Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core.

It shares common functions with the PCIe DesignWare core driver and

inherits common properties defined in

Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.



Additional properties are described here:



Required properties:

- compatible:

	should contain :

	- "amlogic,axg-pcie" for AXG SoC Family

	- "amlogic,g12a-pcie" for G12A SoC Family

	to identify the core.

- reg:

	should contain the configuration address space.

- reg-names: Must be

	- "elbi"	External local bus interface registers

	- "cfg"		Meson specific registers

	- "config"	PCIe configuration space

- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.

- clocks: Must contain an entry for each entry in clock-names.

- clock-names: Must include the following entries:

	- "pclk"       PCIe GEN 100M PLL clock

	- "port"       PCIe_x(A or B) RC clock gate

	- "general"    PCIe Phy clock

- resets: phandle to the reset lines.

- reset-names: must contain "port" and "apb"

       - "port"        Port A or B reset

       - "apb"         Share APB reset

- phys: should contain a phandle to the PCIE phy

- phy-names: must contain "pcie"



- device_type:

	should be "pci". As specified in snps,dw-pcie.yaml





Example configuration:



	pcie: pcie@f9800000 {

			compatible = "amlogic,axg-pcie", "snps,dw-pcie";

			reg = <0x0 0xf9800000 0x0 0x400000

					0x0 0xff646000 0x0 0x2000

					0x0 0xf9f00000 0x0 0x100000>;

			reg-names = "elbi", "cfg", "config";

			reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;

			interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0>;

			interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;

			bus-range = <0x0 0xff>;

			#address-cells = <3>;

			#size-cells = <2>;

			device_type = "pci";

			ranges = <0x82000000 0 0 0x0 0xf9c00000 0 0x00300000>;



			clocks = <&clkc CLKID_USB

					&clkc CLKID_PCIE_A

					&clkc CLKID_PCIE_CML_EN0>;

			clock-names = "general",

					"pclk",

					"port";

			resets = <&reset RESET_PCIE_A>,

				<&reset RESET_PCIE_APB>;

			reset-names = "port",

					"apb";

			phys = <&pcie_phy>;

			phy-names = "pcie";

	};

Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-common.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale i.MX6 PCIe RC/EP controller



maintainers:

  - Lucas Stach <l.stach@pengutronix.de>

  - Richard Zhu <hongxing.zhu@nxp.com>



description:

  Generic Freescale i.MX PCIe Root Port and Endpoint controller

  properties.



properties:

  clocks:

    minItems: 3

    items:

      - description: PCIe bridge clock.

      - description: PCIe bus clock.

      - description: PCIe PHY clock.

      - description: Additional required clock entry for imx6sx-pcie,

           imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.



  clock-names:

    minItems: 3

    items:

      - const: pcie

      - const: pcie_bus

      - enum: [ pcie_phy, pcie_aux ]

      - enum: [ pcie_inbound_axi, pcie_aux ]



  num-lanes:

    const: 1



  fsl,imx7d-pcie-phy:

    $ref: /schemas/types.yaml#/definitions/phandle

    description: A phandle to an fsl,imx7d-pcie-phy node. Additional

      required properties for imx7d-pcie, imx7d-pcie-ep, imx8mq-pcie,

      and imx8mq-pcie-ep.



  power-domains:

    minItems: 1

    items:

      - description: The phandle pointing to the DISPLAY domain for

          imx6sx-pcie, imx6sx-pcie-ep, to PCIE_PHY power domain for

          imx7d-pcie, imx7d-pcie-ep, imx8mq-pcie and imx8mq-pcie-ep.

      - description: The phandle pointing to the PCIE_PHY power domains

          for imx6sx-pcie and imx6sx-pcie-ep.



  power-domain-names:

    minItems: 1

    items:

      - const: pcie

      - const: pcie_phy



  resets:

    minItems: 2

    maxItems: 3

    description: Phandles to PCIe-related reset lines exposed by SRC

      IP block. Additional required by imx7d-pcie, imx7d-pcie-ep,

      imx8mq-pcie, and imx8mq-pcie-ep.



  reset-names:

    minItems: 2

    maxItems: 3



  fsl,tx-deemph-gen1:

    description: Gen1 De-emphasis value (optional required).

    $ref: /schemas/types.yaml#/definitions/uint32

    default: 0



  fsl,tx-deemph-gen2-3p5db:

    description: Gen2 (3.5db) De-emphasis value (optional required).

    $ref: /schemas/types.yaml#/definitions/uint32

    default: 0



  fsl,tx-deemph-gen2-6db:

    description: Gen2 (6db) De-emphasis value (optional required).

    $ref: /schemas/types.yaml#/definitions/uint32

    default: 20



  fsl,tx-swing-full:

    description: Gen2 TX SWING FULL value (optional required).

    $ref: /schemas/types.yaml#/definitions/uint32

    default: 127



  fsl,tx-swing-low:

    description: TX launch amplitude swing_low value (optional required).

    $ref: /schemas/types.yaml#/definitions/uint32

    default: 127



  fsl,max-link-speed:

    description: Specify PCI Gen for link capability (optional required).

      Note that the IMX6 LVDS clock outputs do not meet gen2 jitter

      requirements and thus for gen2 capability a gen2 compliant clock

      generator should be used and configured.

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [1, 2, 3, 4]

    default: 1



  phys:

    maxItems: 1



  phy-names:

    const: pcie-phy



  vpcie-supply:

    description: Should specify the regulator in charge of PCIe port power.

      The regulator will be enabled when initializing the PCIe host and

      disabled either as part of the init process or when shutting down

      the host (optional required).



  vph-supply:

    description: Should specify the regulator in charge of VPH one of

      the three PCIe PHY powers. This regulator can be supplied by both

      1.8v and 3.3v voltage supplies (optional required).



required:

  - clocks

  - clock-names

  - num-lanes



allOf:

  - if:

      properties:

        compatible:

          contains:

            enum:

              - fsl,imx6sx-pcie

              - fsl,imx6sx-pcie-ep

    then:

      properties:

        clock-names:

          items:

            - {}

            - {}

            - const: pcie_phy

            - const: pcie_inbound_axi

        power-domains:

          minItems: 2

        power-domain-names:

          minItems: 2



  - if:

      properties:

        compatible:

          contains:

            enum:

              - fsl,imx8mq-pcie

              - fsl,imx8mq-pcie-ep

    then:

      properties:

        clock-names:

          items:

            - {}

            - {}

            - const: pcie_phy

            - const: pcie_aux

  - if:

      properties:

        compatible:

          not:

            contains:

              enum:

                - fsl,imx6sx-pcie

                - fsl,imx8mq-pcie

                - fsl,imx6sx-pcie-ep

                - fsl,imx8mq-pcie-ep

    then:

      properties:

        clocks:

          maxItems: 3

        clock-names:

          maxItems: 3



  - if:

      properties:

        compatible:

          contains:

            enum:

              - fsl,imx6q-pcie

              - fsl,imx6qp-pcie

              - fsl,imx7d-pcie

              - fsl,imx6q-pcie-ep

              - fsl,imx6qp-pcie-ep

              - fsl,imx7d-pcie-ep

    then:

      properties:

        clock-names:

          maxItems: 3

          contains:

            const: pcie_phy



  - if:

      properties:

        compatible:

          contains:

            enum:

              - fsl,imx8mm-pcie

              - fsl,imx8mp-pcie

              - fsl,imx8mm-pcie-ep

              - fsl,imx8mp-pcie-ep

    then:

      properties:

        clock-names:

          maxItems: 3

          contains:

            const: pcie_aux

  - if:

      properties:

        compatible:

          contains:

            enum:

              - fsl,imx6q-pcie

              - fsl,imx6qp-pcie

              - fsl,imx6q-pcie-ep

              - fsl,imx6qp-pcie-ep

    then:

      properties:

        power-domains: false

        power-domain-names: false



  - if:

      not:

        properties:

          compatible:

            contains:

              enum:

                - fsl,imx6sx-pcie

                - fsl,imx6q-pcie

                - fsl,imx6qp-pcie

                - fsl,imx6sx-pcie-ep

                - fsl,imx6q-pcie-ep

                - fsl,imx6qp-pcie-ep

    then:

      properties:

        power-domains:

          maxItems: 1

        power-domain-names: false



  - if:

      properties:

        compatible:

          contains:

            enum:

              - fsl,imx6q-pcie

              - fsl,imx6sx-pcie

              - fsl,imx6qp-pcie

              - fsl,imx7d-pcie

              - fsl,imx8mq-pcie

              - fsl,imx6q-pcie-ep

              - fsl,imx6sx-pcie-ep

              - fsl,imx6qp-pcie-ep

              - fsl,imx7d-pcie-ep

              - fsl,imx8mq-pcie-ep

    then:

      properties:

        resets:

          minItems: 3

        reset-names:

          items:

            - const: pciephy

            - const: apps

            - const: turnoff

    else:

      properties:

        resets:

          maxItems: 2

        reset-names:

          items:

            - const: apps

            - const: turnoff



additionalProperties: true



...

Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale i.MX6 PCIe Endpoint controller



maintainers:

  - Lucas Stach <l.stach@pengutronix.de>

  - Richard Zhu <hongxing.zhu@nxp.com>



description: |+

  This PCIe controller is based on the Synopsys DesignWare PCIe IP and

  thus inherits all the common properties defined in snps,dw-pcie-ep.yaml.

  The controller instances are dual mode where in they can work either in

  Root Port mode or Endpoint mode but one at a time.



properties:

  compatible:

    enum:

      - fsl,imx8mm-pcie-ep

      - fsl,imx8mq-pcie-ep

      - fsl,imx8mp-pcie-ep



  reg:

    minItems: 2



  reg-names:

    items:

      - const: dbi

      - const: addr_space



  interrupts:

    items:

      - description: builtin eDMA interrupter.



  interrupt-names:

    items:

      - const: dma



required:

  - compatible

  - reg

  - reg-names

  - interrupts

  - interrupt-names



allOf:

  - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#

  - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/imx8mp-clock.h>

    #include <dt-bindings/power/imx8mp-power.h>

    #include <dt-bindings/reset/imx8mp-reset.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    pcie_ep: pcie-ep@33800000 {

      compatible = "fsl,imx8mp-pcie-ep";

      reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>;

      reg-names = "dbi", "addr_space";

      clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,

               <&clk IMX8MP_CLK_HSIO_AXI>,

               <&clk IMX8MP_CLK_PCIE_ROOT>;

      clock-names = "pcie", "pcie_bus", "pcie_aux";

      assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;

      assigned-clock-rates = <10000000>;

      assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;

      num-lanes = <1>;

      interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */

      interrupt-names = "dma";

      fsl,max-link-speed = <3>;

      power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;

      resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,

               <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;

      reset-names = "apps", "turnoff";

      phys = <&pcie_phy>;

      phy-names = "pcie-phy";

      num-ib-windows = <4>;

      num-ob-windows = <4>;

    };