Commit 098fde11 authored by chas williams - CONTRACTOR's avatar chas williams - CONTRACTOR Committed by David S. Miller
Browse files

atm: [nicstar] reformatted with Lindent 



Signed-off-by: default avatarChas Williams - CONTRACTOR <chas@cmf.nrl.navy.mil>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 741a00be

drivers/atm/nicstar.c

+2465 −2650

File changed.

Preview size limit exceeded, changes collapsed.

drivers/atm/nicstar.h

+255 −323
Original line number Diff line number Diff line 
/******************************************************************************

 *

/*

 * nicstar.h

 *

 * Header file for the nicstar device driver.
@@ -8,15 +7,12 @@ 
 * PowerPC support by Jay Talbott (jay_talbott@mcg.mot.com) April 1999

 *

 * (C) INESC 1998

 *

 ******************************************************************************/



 */



#ifndef _LINUX_NICSTAR_H_

#define _LINUX_NICSTAR_H_





/* Includes *******************************************************************/

/* Includes */



#include <linux/types.h>

#include <linux/pci.h>
@@ -25,8 +21,7 @@ 
#include <linux/atmdev.h>

#include <linux/atm_nicstar.h>





/* Options ********************************************************************/

/* Options */



#define NS_MAX_CARDS 4		/* Maximum number of NICStAR based cards

				   controlled by the device driver. Must
@@ -77,7 +72,6 @@ 
#define TOP_HB 64

#define TOP_IOVB 256





#define MAX_TBD_PER_VC 1	/* Number of TBDs before a TSR */

#define MAX_TBD_PER_SCQ 10	/* Only meaningful for variable rate SCQs */
@@ -89,15 +83,12 @@ 


#define PCR_TOLERANCE (1.0001)







/* ESI stuff ******************************************************************/

/* ESI stuff */



#define NICSTAR_EPROM_MAC_ADDR_OFFSET 0x6C

#define NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT 0xF6





/* #defines *******************************************************************/

/* #defines */



#define NS_IOREMAP_SIZE 4096
@@ -123,18 +114,15 @@ 
#define NS_SMSKBSIZE (NS_SMBUFSIZE + NS_AAL0_HEADER)

#define NS_LGSKBSIZE (NS_SMBUFSIZE + NS_LGBUFSIZE)



/* NICStAR structures located in host memory */



/* NICStAR structures located in host memory **********************************/







/* RSQ - Receive Status Queue 

/*

 * RSQ - Receive Status Queue

 *

 * Written by the NICStAR, read by the device driver.

 */



typedef struct ns_rsqe

{

typedef struct ns_rsqe {

	u32 word_1;

	u32 buffer_handle;

	u32 final_aal5_crc32;
@@ -180,20 +168,17 @@ typedef struct ns_rsqe 
#define NS_RSQ_NUM_ENTRIES (NS_RSQSIZE / 16)

#define NS_RSQ_ALIGNMENT NS_RSQSIZE







/* RCQ - Raw Cell Queue

/*

 * RCQ - Raw Cell Queue

 *

 * Written by the NICStAR, read by the device driver.

 */



typedef struct cell_payload

{

typedef struct cell_payload {

	u32 word[12];

} cell_payload;



typedef struct ns_rcqe

{

typedef struct ns_rcqe {

	u32 word_1;

	u32 word_2;

	u32 word_3;
@@ -210,15 +195,13 @@ typedef struct ns_rcqe 
#define ns_rcqe_nextbufhandle(ns_rcqep) \

        (le32_to_cpu((ns_rcqep)->word_2))







/* SCQ - Segmentation Channel Queue 

/*

 * SCQ - Segmentation Channel Queue

 *

 * Written by the device driver, read by the NICStAR.

 */



typedef struct ns_scqe

{

typedef struct ns_scqe {

	u32 word_1;

	u32 word_2;

	u32 word_3;
@@ -231,7 +214,6 @@ typedef struct ns_scqe 
#define NS_SCQE_TYPE_TBD 0x00000000

#define NS_SCQE_TYPE_TSR 0x80000000





#define NS_TBD_EOPDU 0x40000000

#define NS_TBD_AAL0  0x00000000

#define NS_TBD_AAL34 0x04000000
@@ -253,7 +235,6 @@ typedef struct ns_scqe 
#define ns_tbd_mkword_4(gfc, vpi, vci, pt, clp) \

      (cpu_to_le32((gfc) << 28 | (vpi) << 20 | (vci) << 4 | (pt) << 1 | (clp)))





#define NS_TSR_INTENABLE 0x20000000



#define NS_TSR_SCDISVBR 0xFFFF	/* Use as scdi for VBR SCD */
@@ -273,15 +254,13 @@ typedef struct ns_scqe 


#define NS_SCQE_SIZE 16







/* TSQ - Transmit Status Queue

/*

 * TSQ - Transmit Status Queue

 *

 * Written by the NICStAR, read by the device driver.

 */



typedef struct ns_tsi

{

typedef struct ns_tsi {

	u32 word_1;

	u32 word_2;

} ns_tsi;
@@ -301,12 +280,10 @@ typedef struct ns_tsi 
#define ns_tsi_init(ns_tsip) \

        ((ns_tsip)->word_2 = cpu_to_le32(NS_TSI_EMPTY))





#define NS_TSQSIZE 8192

#define NS_TSQ_NUM_ENTRIES 1024

#define NS_TSQ_ALIGNMENT 8192





#define NS_TSI_SCDISVBR NS_TSR_SCDISVBR



#define ns_tsi_tmrof(ns_tsip) \
@@ -316,19 +293,15 @@ typedef struct ns_tsi 
#define ns_tsi_getscqpos(ns_tsip) \

        (le32_to_cpu((ns_tsip)->word_1) & 0x00007FFF)



/* NICStAR structures located in local SRAM */





/* NICStAR structures located in local SRAM ***********************************/







/* RCT - Receive Connection Table

/*

 * RCT - Receive Connection Table

 *

 * Written by both the NICStAR and the device driver.

 */



typedef struct ns_rcte

{

typedef struct ns_rcte {

	u32 word_1;

	u32 buffer_handle;

	u32 dma_address;
@@ -360,23 +333,19 @@ typedef struct ns_rcte 
   /* NOTE: We could make macros to contruct the first word of the RCTE,

      but that doesn't seem to make much sense... */







/* FBD - Free Buffer Descriptor

/*

 * FBD - Free Buffer Descriptor

 *

 * Written by the device driver using via the command register.

 */



typedef struct ns_fbd

{

typedef struct ns_fbd {

	u32 buffer_handle;

	u32 dma_address;

} ns_fbd;









/* TST - Transmit Schedule Table

/*

 * TST - Transmit Schedule Table

 *

 * Written by the device driver.

 */
@@ -400,15 +369,13 @@ typedef u32 ns_tste; 
      location of the next TST entry to read.

    */







/* SCD - Segmentation Channel Descriptor

/*

 * SCD - Segmentation Channel Descriptor

 *

 * Written by both the device driver and the NICStAR

 */



typedef struct ns_scd

{

typedef struct ns_scd {

	u32 word_1;

	u32 word_2;

	u32 partial_aal5_crc;
@@ -428,11 +395,7 @@ typedef struct ns_scd 
   /* NOTE: There are other fields in word 2 of the SCD, but as they should

      not be needed in the device driver they are not defined here. */









/* NICStAR local SRAM memory map **********************************************/



/* NICStAR local SRAM memory map */



#define NS_RCT           0x00000

#define NS_RCT_32_END    0x03FFF
@@ -455,15 +418,11 @@ typedef struct ns_scd 
#define NS_LGFBQ         0x1FC00

#define NS_LGFBQ_END     0x1FFFF







/* NISCtAR operation registers ************************************************/



/* NISCtAR operation registers */



/* See Section 3.4 of `IDT77211 NICStAR User Manual' from www.idt.com */



enum ns_regs

{

enum ns_regs {

	DR0 = 0x00,		/* Data Register 0 R/W */

	DR1 = 0x04,		/* Data Register 1 W */

	DR2 = 0x08,		/* Data Register 2 W */
@@ -487,9 +446,7 @@ enum ns_regs 
	VPM = 0x50		/* VPI/VCI Mask W */

};





/* NICStAR commands issued to the CMD register ********************************/



/* NICStAR commands issued to the CMD register */



/* Top 4 bits are command opcode, lower 28 are parameters. */
@@ -517,8 +474,7 @@ enum ns_regs 
#define NS_CMD_OPEN_CONNECTION (NS_CMD_OPENCLOSE_CONNECTION | 0x00080000)

#define NS_CMD_CLOSE_CONNECTION NS_CMD_OPENCLOSE_CONNECTION





/* NICStAR configuration bits *************************************************/

/* NICStAR configuration bits */



#define NS_CFG_SWRST          0x80000000	/* Software Reset */

#define NS_CFG_RXPATH         0x20000000	/* Receive Path Enable */
@@ -579,8 +535,7 @@ enum ns_regs 
#define NS_CFG_RXINT_624US   0x00003000

#define NS_CFG_RXINT_899US   0x00004000





/* NICStAR STATus bits ********************************************************/

/* NICStAR STATus bits */



#define NS_STAT_SFBQC_MASK 0xFF000000	/* hi 8 bits Small Buffer Queue Count */

#define NS_STAT_LFBQC_MASK 0x00FF0000	/* hi 8 bits Large Buffer Queue Count */
@@ -602,10 +557,7 @@ enum ns_regs 
#define ns_stat_sfbqc_get(stat) (((stat) & NS_STAT_SFBQC_MASK) >> 23)

#define ns_stat_lfbqc_get(stat) (((stat) & NS_STAT_LFBQC_MASK) >> 15)







/* #defines which depend on other #defines ************************************/



/* #defines which depend on other #defines */



#define NS_TST0 NS_TST_FRSCD

#define NS_TST1 (NS_TST_FRSCD + NS_TST_NUM_ENTRIES + 1)
@@ -672,8 +624,7 @@ enum ns_regs 
#define NS_CFG_TSQFIE_OPT 0x00000000

#endif /* ENABLE_TSQFIE */





/* PCI stuff ******************************************************************/

/* PCI stuff */



#ifndef PCI_VENDOR_ID_IDT

#define PCI_VENDOR_ID_IDT 0x111D
@@ -683,10 +634,7 @@ enum ns_regs 
#define PCI_DEVICE_ID_IDT_IDT77201 0x0001

#endif /* PCI_DEVICE_ID_IDT_IDT77201 */







/* Device driver structures ***************************************************/



/* Device driver structures */



struct ns_skb_cb {

	u32 buf_type;		/* BUF_SM/BUF_LG/BUF_NONE */
@@ -694,17 +642,14 @@ struct ns_skb_cb { 


#define NS_SKB_CB(skb)	((struct ns_skb_cb *)((skb)->cb))



typedef struct tsq_info

{

typedef struct tsq_info {

	void *org;

	ns_tsi *base;

	ns_tsi *next;

	ns_tsi *last;

} tsq_info;





typedef struct scq_info

{

typedef struct scq_info {

	void *org;

	ns_scqe *base;

	ns_scqe *last;
@@ -721,19 +666,14 @@ typedef struct scq_info 
	spinlock_t lock;	/* SCQ spinlock */

} scq_info;







typedef struct rsq_info

{

typedef struct rsq_info {

	void *org;

	ns_rsqe *base;

	ns_rsqe *next;

	ns_rsqe *last;

} rsq_info;





typedef struct skb_pool

{

typedef struct skb_pool {

	volatile int count;	/* number of buffers in the queue */

	struct sk_buff_head queue;

} skb_pool;
@@ -742,9 +682,7 @@ typedef struct skb_pool 
         actual value used for buffer management is the one read from the

	 card. */





typedef struct vc_map

{

typedef struct vc_map {

	volatile unsigned int tx:1;	/* TX vc? */

	volatile unsigned int rx:1;	/* RX vc? */

	struct atm_vcc *tx_vcc, *rx_vcc;
@@ -755,18 +693,14 @@ typedef struct vc_map 
	int tbd_count;

} vc_map;





struct ns_skb_data

{

struct ns_skb_data {

	struct atm_vcc *vcc;

	int iovcnt;

};



#define NS_SKB(skb) (((struct ns_skb_data *) (skb)->cb))





typedef struct ns_dev

{

typedef struct ns_dev {

	int index;		/* Card ID to the device driver */

	int sram_size;		/* In k x 32bit words. 32 or 128 */

	void __iomem *membase;	/* Card's memory base address */
@@ -806,7 +740,6 @@ typedef struct ns_dev 
	spinlock_t res_lock;	/* Card resource lock */

} ns_dev;





   /* NOTE: Each tste2vc entry relates a given TST entry to the corresponding

      CBR vc. If the entry is not allocated, it must be NULL.
@@ -816,5 +749,4 @@ typedef struct ns_dev 
      scd2vc allows us to find out unused fixed rate SCDs, because

      they must have a NULL pointer here. */





#endif /* _LINUX_NICSTAR_H_ */

drivers/atm/nicstarmac.c

+168 −196
Original line number Diff line number Diff line
@@ -13,15 +13,15 @@ typedef void __iomem *virt_addr_t; 


#define CYCLE_DELAY 5



/* This was the original definition

/*

   This was the original definition

#define osp_MicroDelay(microsec) \

    do { int _i = 4*microsec; while (--_i > 0) { __SLOW_DOWN_IO; }} while (0)

*/

#define osp_MicroDelay(microsec) {unsigned long useconds = (microsec); \

                                  udelay((useconds));}





/* The following tables represent the timing diagrams found in

/*

 * The following tables represent the timing diagrams found in

 * the Data Sheet for the Xicor X25020 EEProm.  The #defines below

 * represent the bits in the NICStAR's General Purpose register

 * that must be toggled for the corresponding actions on the EEProm
@@ -40,8 +40,7 @@ typedef void __iomem *virt_addr_t; 


/* Read Status Register = 0000 0101b */

#if 0

static u_int32_t rdsrtab[] =

{

static u_int32_t rdsrtab[] = {

	CS_HIGH | CLK_HIGH,

	CS_LOW | CLK_LOW,

	CLK_HIGH,		/* 0 */
@@ -62,10 +61,8 @@ static u_int32_t rdsrtab[] = 
};

#endif /*  0  */





/* Read from EEPROM = 0000 0011b */

static u_int32_t readtab[] =

{

static u_int32_t readtab[] = {

	/*

	   CS_HIGH | CLK_HIGH,

	 */
@@ -87,10 +84,8 @@ static u_int32_t readtab[] = 
	CLK_HIGH | SI_HIGH	/* 1 */

};





/* Clock to read from/write to the eeprom */

static u_int32_t clocktab[] =

{	

static u_int32_t clocktab[] = {

	CLK_LOW,

	CLK_HIGH,

	CLK_LOW,
@@ -110,7 +105,6 @@ static u_int32_t clocktab[] = 
	CLK_LOW

};





#define NICSTAR_REG_WRITE(bs, reg, val) \

	while ( readl(bs + STAT) & 0x0200 ) ; \

	writel((val),(base)+(reg))
@@ -124,8 +118,7 @@ static u_int32_t clocktab[] = 
 * register.  

 */

#if 0

u_int32_t

nicstar_read_eprom_status( virt_addr_t base )

u_int32_t nicstar_read_eprom_status(virt_addr_t base)

{

	u_int32_t val;

	u_int32_t rbyte;
@@ -134,8 +127,7 @@ nicstar_read_eprom_status( virt_addr_t base ) 
	/* Send read instruction */

	val = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0;



   for (i=0; i<ARRAY_SIZE(rdsrtab); i++)

   {

	for (i = 0; i < ARRAY_SIZE(rdsrtab); i++) {

		NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,

				  (val | rdsrtab[i]));

		osp_MicroDelay(CYCLE_DELAY);
@@ -145,8 +137,7 @@ nicstar_read_eprom_status( virt_addr_t base ) 
	/* Data clocked out of eeprom on falling edge of clock */



	rbyte = 0;

   for (i=7, j=0; i>=0; i--)

   {

	for (i = 7, j = 0; i >= 0; i--) {

		NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,

				  (val | clocktab[j++]));

		rbyte |= (((NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE)
@@ -161,15 +152,13 @@ nicstar_read_eprom_status( virt_addr_t base ) 
}

#endif /*  0  */





/*

 * This routine will clock the Read_data function into the X2520

 * eeprom, followed by the address to read from, through the NicSTaR's General

 * Purpose register.  

 */



static u_int8_t 

read_eprom_byte(virt_addr_t base, u_int8_t offset)

static u_int8_t read_eprom_byte(virt_addr_t base, u_int8_t offset)

{

	u_int32_t val = 0;

	int i, j = 0;
@@ -178,16 +167,14 @@ read_eprom_byte(virt_addr_t base, u_int8_t offset) 
	val = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0;



	/* Send READ instruction */

   for (i=0; i<ARRAY_SIZE(readtab); i++)

   {

	for (i = 0; i < ARRAY_SIZE(readtab); i++) {

		NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,

				  (val | readtab[i]));

		osp_MicroDelay(CYCLE_DELAY);

	}



	/* Next, we need to send the byte address to read from */

   for (i=7; i>=0; i--)

   {

	for (i = 7; i >= 0; i--) {

		NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,

				  (val | clocktab[j++] | ((offset >> i) & 1)));

		osp_MicroDelay(CYCLE_DELAY);
@@ -199,12 +186,12 @@ read_eprom_byte(virt_addr_t base, u_int8_t offset) 
	j = 0;



	/* Now, we can read data from the eeprom by clocking it in */

   for (i=7; i>=0; i--)

   {

	for (i = 7; i >= 0; i--) {

		NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,

				  (val | clocktab[j++]));

		osp_MicroDelay(CYCLE_DELAY);

      tempread |= (((NICSTAR_REG_READ( base, NICSTAR_REG_GENERAL_PURPOSE )

		tempread |=

		    (((NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE)

		       & 0x00010000) >> 16) << i);

		NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,

				  (val | clocktab[j++]));
@@ -216,9 +203,7 @@ read_eprom_byte(virt_addr_t base, u_int8_t offset) 
	return tempread;

}





static void

nicstar_init_eprom( virt_addr_t base )

static void nicstar_init_eprom(virt_addr_t base)

{

	u_int32_t val;
@@ -244,33 +229,20 @@ nicstar_init_eprom( virt_addr_t base ) 
	osp_MicroDelay(CYCLE_DELAY);

}





/*

 * This routine will be the interface to the ReadPromByte function

 * above.

 */



static void

nicstar_read_eprom(

    virt_addr_t	base,

    u_int8_t	prom_offset,

    u_int8_t	*buffer,

    u_int32_t	nbytes )

nicstar_read_eprom(virt_addr_t base,

		   u_int8_t prom_offset, u_int8_t * buffer, u_int32_t nbytes)

{

	u_int i;



    for (i=0; i<nbytes; i++)

    {

	for (i = 0; i < nbytes; i++) {

		buffer[i] = read_eprom_byte(base, prom_offset);

		++prom_offset;

		osp_MicroDelay(CYCLE_DELAY);

	}

}
 




/*

void osp_MicroDelay(int x) {

    

}

*/