Commit 09821499 authored by Igor Kravchenko's avatar Igor Kravchenko Committed by Alex Deucher
Browse files

drm/amd/display: Read VBIOS Golden Settings Tbl 



[Why]
For ver.4.4 and higher VBIOS contains default setting table.

{How]
Read Golden Settings Table from VBIOS, apply Aux tuning parameters.

Signed-off-by: default avatarIgor Kravchenko <Igor.Kravchenko@amd.com>
Reviewed-by: default avatarAric Cyr <Aric.Cyr@amd.com>
Acked-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c06f670f

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

+2 −0
Original line number Diff line number Diff line
@@ -2834,6 +2834,8 @@ static const struct dc_vbios_funcs vbios_funcs = { 
	.bios_parser_destroy = bios_parser_destroy,



	.get_board_layout_info = bios_get_board_layout_info,



	.get_atom_dc_golden_table = NULL

};



static bool bios_parser_construct(

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

+81 −0
Original line number Diff line number Diff line
@@ -2079,6 +2079,85 @@ static uint16_t bios_parser_pack_data_tables( 
	return 0;

}



static struct atom_dc_golden_table_v1 *bios_get_golden_table(

		struct bios_parser *bp,

		uint32_t rev_major,

		uint32_t rev_minor,

		uint16_t *dc_golden_table_ver)

{

	struct atom_display_controller_info_v4_4 *disp_cntl_tbl_4_4 = NULL;

	uint32_t dc_golden_offset = 0;

	*dc_golden_table_ver = 0;



	if (!DATA_TABLES(dce_info))

		return NULL;



	/* ver.4.4 or higher */

	switch (rev_major) {

	case 4:

		switch (rev_minor) {

		case 4:

			disp_cntl_tbl_4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4,

									DATA_TABLES(dce_info));

			if (!disp_cntl_tbl_4_4)

				return NULL;

			dc_golden_offset = disp_cntl_tbl_4_4->dc_golden_table_offset;

			*dc_golden_table_ver = disp_cntl_tbl_4_4->dc_golden_table_ver;

			break;

		}

		break;

	}



	if (!dc_golden_offset)

		return NULL;



	if (*dc_golden_table_ver != 1)

		return NULL;



	return GET_IMAGE(struct atom_dc_golden_table_v1,

					 dc_golden_offset);

}



static enum bp_result bios_get_atom_dc_golden_table(

	struct dc_bios *dcb)

{

	struct bios_parser *bp = BP_FROM_DCB(dcb);

	enum bp_result result = BP_RESULT_OK;

	struct atom_dc_golden_table_v1 *atom_dc_golden_table = NULL;

	struct atom_common_table_header *header;

	struct atom_data_revision tbl_revision;

	uint16_t dc_golden_table_ver = 0;



	header = GET_IMAGE(struct atom_common_table_header,

							DATA_TABLES(dce_info));

	if (!header)

		return BP_RESULT_UNSUPPORTED;



	get_atom_data_table_revision(header, &tbl_revision);



	atom_dc_golden_table = bios_get_golden_table(bp,

			tbl_revision.major,

			tbl_revision.minor,

			&dc_golden_table_ver);



	if (!atom_dc_golden_table)

		return BP_RESULT_UNSUPPORTED;



	dcb->golden_table.dc_golden_table_ver = dc_golden_table_ver;

	dcb->golden_table.aux_dphy_rx_control0_val = atom_dc_golden_table->aux_dphy_rx_control0_val;

	dcb->golden_table.aux_dphy_rx_control1_val = atom_dc_golden_table->aux_dphy_rx_control1_val;

	dcb->golden_table.aux_dphy_tx_control_val = atom_dc_golden_table->aux_dphy_tx_control_val;

	dcb->golden_table.dc_gpio_aux_ctrl_0_val = atom_dc_golden_table->dc_gpio_aux_ctrl_0_val;

	dcb->golden_table.dc_gpio_aux_ctrl_1_val = atom_dc_golden_table->dc_gpio_aux_ctrl_1_val;

	dcb->golden_table.dc_gpio_aux_ctrl_2_val = atom_dc_golden_table->dc_gpio_aux_ctrl_2_val;

	dcb->golden_table.dc_gpio_aux_ctrl_3_val = atom_dc_golden_table->dc_gpio_aux_ctrl_3_val;

	dcb->golden_table.dc_gpio_aux_ctrl_4_val = atom_dc_golden_table->dc_gpio_aux_ctrl_4_val;

	dcb->golden_table.dc_gpio_aux_ctrl_5_val = atom_dc_golden_table->dc_gpio_aux_ctrl_5_val;



	return result;

}





static const struct dc_vbios_funcs vbios_funcs = {

	.get_connectors_number = bios_parser_get_connectors_number,
@@ -2128,6 +2207,8 @@ static const struct dc_vbios_funcs vbios_funcs = { 


	.get_board_layout_info = bios_get_board_layout_info,

	.pack_data_tables = bios_parser_pack_data_tables,



	.get_atom_dc_golden_table = bios_get_atom_dc_golden_table

};



static bool bios_parser2_construct(

drivers/gpu/drm/amd/display/dc/core/dc_link.c

+3 −0
Original line number Diff line number Diff line
@@ -1540,6 +1540,9 @@ static bool dc_link_construct(struct dc_link *link, 
		}

	}



	if (bios->funcs->get_atom_dc_golden_table)

		bios->funcs->get_atom_dc_golden_table(bios);



	/*

	 * TODO check if GPIO programmed correctly

	 *

drivers/gpu/drm/amd/display/dc/dc_bios_types.h

+4 −0
Original line number Diff line number Diff line
@@ -133,6 +133,9 @@ struct dc_vbios_funcs { 
	uint16_t (*pack_data_tables)(

		struct dc_bios *dcb,

		void *dst);



	enum bp_result (*get_atom_dc_golden_table)(

			struct dc_bios *dcb);

};



struct bios_registers {
@@ -154,6 +157,7 @@ struct dc_bios { 
	struct dc_firmware_info fw_info;

	bool fw_info_valid;

	struct dc_vram_info vram_info;

	struct dc_golden_table golden_table;

};



#endif /* DC_BIOS_TYPES_H */

drivers/gpu/drm/amd/display/dc/dc_types.h

+14 −0
Original line number Diff line number Diff line
@@ -890,6 +890,20 @@ struct dsc_dec_dpcd_caps { 
	uint32_t branch_max_line_width;

};



struct dc_golden_table {

	uint16_t dc_golden_table_ver;

	uint32_t aux_dphy_rx_control0_val;

	uint32_t aux_dphy_tx_control_val;

	uint32_t aux_dphy_rx_control1_val;

	uint32_t dc_gpio_aux_ctrl_0_val;

	uint32_t dc_gpio_aux_ctrl_1_val;

	uint32_t dc_gpio_aux_ctrl_2_val;

	uint32_t dc_gpio_aux_ctrl_3_val;

	uint32_t dc_gpio_aux_ctrl_4_val;

	uint32_t dc_gpio_aux_ctrl_5_val;

};





#if defined(CONFIG_DRM_AMD_DC_DCN3_0)

enum dc_gpu_mem_alloc_type {

	DC_MEM_ALLOC_TYPE_GART,