Commit 095730dd authored by Peng Fan's avatar Peng Fan Committed by Jassi Brar
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dt-bindings: mailbox: imx-mu: add RST channel 



i.MX MU has a MUR bit which is to reset both the Processor B and the
Processor A sides of the MU module, forcing all control and status
registers to return to their default values (except the BHR bit in the ACR
register and BHRM bit in BCR register), and all internal states to be
cleared.

Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarJassi Brar <jaswinder.singh@linaro.org>
parent 60545466

Documentation/devicetree/bindings/mailbox/fsl,mu.yaml

+4 −2
Original line number Diff line number Diff line
@@ -72,14 +72,16 @@ properties: 
      type      : Channel type

      channel   : Channel number



      This MU support 4 type of unidirectional channels, each type

      has 4 channels. A total of 16 channels. Following types are

      This MU support 5 type of unidirectional channels, each type

      has 4 channels except RST channel which only has 1 channel.

      A total of 17 channels.  Following types are

      supported:

      0 - TX channel with 32bit transmit register and IRQ transmit

          acknowledgment support.

      1 - RX channel with 32bit receive register and IRQ support

      2 - TX doorbell channel. Without own register and no ACK support.

      3 - RX doorbell channel.

      4 - RST channel

    const: 2



  clocks: