Merge tag 'amd-drm-fixes-5.19-2022-07-13' of... (093f8d8f) · Commits · EulixOS / Software / Kernel

drivers/gpu/drm/amd/amdkfd/kfd_device.c

+2 −0

Original line number	Diff line number	Diff line
		@@ -184,6 +184,8 @@ static void kfd_device_info_init(struct kfd_dev *kfd,
		/* Navi2x+, Navi1x+ */
		if (gc_version == IP_VERSION(10, 3, 6))
		kfd->device_info.no_atomic_fw_version = 14;
		else if (gc_version == IP_VERSION(10, 3, 7))
		kfd->device_info.no_atomic_fw_version = 3;
		else if (gc_version >= IP_VERSION(10, 3, 0))
		kfd->device_info.no_atomic_fw_version = 92;
		else if (gc_version >= IP_VERSION(10, 1, 1))

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+80 −4

Original line number	Diff line number	Diff line
		@@ -72,6 +72,7 @@
		#include <linux/pci.h>
		#include <linux/firmware.h>
		#include <linux/component.h>
		#include <linux/dmi.h>

		#include <drm/display/drm_dp_mst_helper.h>
		#include <drm/display/drm_hdmi_helper.h>
		@@ -462,6 +463,26 @@ static void dm_pflip_high_irq(void *interrupt_params)
		vrr_active, (int) !e);
		}

		static void dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc)
		{
		struct drm_crtc *crtc = &acrtc->base;
		struct drm_device *dev = crtc->dev;
		unsigned long flags;

		drm_crtc_handle_vblank(crtc);

		spin_lock_irqsave(&dev->event_lock, flags);

		/* Send completion event for cursor-only commits */
		if (acrtc->event && acrtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
		drm_crtc_send_vblank_event(crtc, acrtc->event);
		drm_crtc_vblank_put(crtc);
		acrtc->event = NULL;
		}

		spin_unlock_irqrestore(&dev->event_lock, flags);
		}

		static void dm_vupdate_high_irq(void *interrupt_params)
		{
		struct common_irq_params *irq_params = interrupt_params;
		@@ -500,7 +521,7 @@ static void dm_vupdate_high_irq(void *interrupt_params)
		* if a pageflip happened inside front-porch.
		*/
		if (vrr_active) {
		drm_crtc_handle_vblank(&acrtc->base);
		dm_crtc_handle_vblank(acrtc);

		/* BTR processing for pre-DCE12 ASICs */
		if (acrtc->dm_irq_params.stream &&
		@@ -552,7 +573,7 @@ static void dm_crtc_high_irq(void *interrupt_params)
		* to dm_vupdate_high_irq after end of front-porch.
		*/
		if (!vrr_active)
		drm_crtc_handle_vblank(&acrtc->base);
		dm_crtc_handle_vblank(acrtc);

		/**
		* Following stuff must happen at start of vblank, for crc
		@@ -1382,6 +1403,41 @@ static bool dm_should_disable_stutter(struct pci_dev *pdev)
		return false;
		}

		static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
		{
		.matches = {
		DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
		DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
		},
		},
		{
		.matches = {
		DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
		DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
		},
		},
		{
		.matches = {
		DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
		DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
		},
		},
		{}
		};

		static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
		{
		const struct dmi_system_id *dmi_id;

		dm->aux_hpd_discon_quirk = false;

		dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
		if (dmi_id) {
		dm->aux_hpd_discon_quirk = true;
		DRM_INFO("aux_hpd_discon_quirk attached\n");
		}
		}

		static int amdgpu_dm_init(struct amdgpu_device *adev)
		{
		struct dc_init_data init_data;
		@@ -1508,6 +1564,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
		}

		INIT_LIST_HEAD(&adev->dm.da_list);

		retrieve_dmi_info(&adev->dm);

		/* Display Core create. */
		adev->dm.dc = dc_create(&init_data);

		@@ -5407,7 +5466,7 @@ fill_blending_from_plane_state(const struct drm_plane_state *plane_state,
		}
		}

		if (per_pixel_alpha && plane_state->pixel_blend_mode == DRM_MODE_BLEND_COVERAGE)
		if (*per_pixel_alpha && plane_state->pixel_blend_mode == DRM_MODE_BLEND_COVERAGE)
		*pre_multiplied_alpha = false;
		}

		@@ -9135,6 +9194,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
		struct amdgpu_bo *abo;
		uint32_t target_vblank, last_flip_vblank;
		bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
		bool cursor_update = false;
		bool pflip_present = false;
		struct {
		struct dc_surface_update surface_updates[MAX_SURFACES];
		@@ -9170,8 +9230,13 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
		struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);

		/* Cursor plane is handled after stream updates */
		if (plane->type == DRM_PLANE_TYPE_CURSOR)
		if (plane->type == DRM_PLANE_TYPE_CURSOR) {
		if ((fb && crtc == pcrtc) \|\|
		(old_plane_state->fb && old_plane_state->crtc == pcrtc))
		cursor_update = true;

		continue;
		}

		if (!fb \|\| !crtc \|\| pcrtc != crtc)
		continue;
		@@ -9334,6 +9399,17 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
		bundle->stream_update.vrr_infopacket =
		&acrtc_state->stream->vrr_infopacket;
		}
		} else if (cursor_update && acrtc_state->active_planes > 0 &&
		!acrtc_state->force_dpms_off &&
		acrtc_attach->base.state->event) {
		drm_crtc_vblank_get(pcrtc);

		spin_lock_irqsave(&pcrtc->dev->event_lock, flags);

		acrtc_attach->event = acrtc_attach->base.state->event;
		acrtc_attach->base.state->event = NULL;

		spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
		}

		/* Update the planes if changed or disable if we don't have any. */

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

+8 −0

Original line number	Diff line number	Diff line
		@@ -540,6 +540,14 @@ struct amdgpu_display_manager {
		* last successfully applied backlight values.
		*/
		u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP];

		/**
		* @aux_hpd_discon_quirk:
		*
		* quirk for hpd discon while aux is on-going.
		* occurred on certain intel platform
		*/
		bool aux_hpd_discon_quirk;
		};

		enum dsc_clock_force_state {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

+17 −0

Original line number	Diff line number	Diff line
		@@ -56,6 +56,8 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
		ssize_t result = 0;
		struct aux_payload payload;
		enum aux_return_code_type operation_result;
		struct amdgpu_device *adev;
		struct ddc_service *ddc;

		if (WARN_ON(msg->size > 16))
		return -E2BIG;
		@@ -74,6 +76,21 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
		result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload,
		&operation_result);

		/*
		* w/a on certain intel platform where hpd is unexpected to pull low during
		* 1st sideband message transaction by return AUX_RET_ERROR_HPD_DISCON
		* aux transaction is succuess in such case, therefore bypass the error
		*/
		ddc = TO_DM_AUX(aux)->ddc_service;
		adev = ddc->ctx->driver_context;
		if (adev->dm.aux_hpd_discon_quirk) {
		if (msg->address == DP_SIDEBAND_MSG_DOWN_REQ_BASE &&
		operation_result == AUX_RET_ERROR_HPD_DISCON) {
		result = 0;
		operation_result = AUX_RET_SUCCESS;
		}
		}

		if (payload.write && result >= 0)
		result = msg->size;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

+6 −5

Original line number	Diff line number	Diff line
		@@ -1117,12 +1117,13 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
		* on certain displays, such as the Sharp 4k. 36bpp is needed
		* to support SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 and
		* SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 with actual > 10 bpc
		* precision on at least DCN display engines. However, at least
		* Carrizo with DCE_VERSION_11_0 does not like 36 bpp lb depth,
		* so use only 30 bpp on DCE_VERSION_11_0. Testing with DCE 11.2 and 8.3
		* did not show such problems, so this seems to be the exception.
		* precision on DCN display engines, but apparently not for DCE, as
		* far as testing on DCE-11.2 and DCE-8 showed. Various DCE parts have
		* problems: Carrizo with DCE_VERSION_11_0 does not like 36 bpp lb depth,
		* neither do DCE-8 at 4k resolution, or DCE-11.2 (broken identify pixel
		* passthrough). Therefore only use 36 bpp on DCN where it is actually needed.
		*/
		if (plane_state->ctx->dce_version > DCE_VERSION_11_0)
		if (plane_state->ctx->dce_version > DCE_VERSION_MAX)
		pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP;
		else
		pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;